KR950004227B1 - Information processing system - Google Patents

Abstract

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Description

Information processing system

1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention.

2 is a block diagram showing the structure of a disk control unit.

3 is an explanatory diagram showing the principle of interrupts to be accepted for each paragraph of a microprogram.

Fig. 4A is a block diagram showing a save and return mechanism of a register.

Fig. 4B is a timing diagram showing operation timing of the register save and return mechanism.

5 is a block diagram showing the configuration of a conventional information processing system.

6 is a block diagram showing the structure of a conventional disk control unit.

* Explanation of symbols for the main parts of the drawings

1: MPU 2: Temporary register group

3: relative flags 8: microprogram memory

10: disk control unit 16: save register group for temporal register group (2)

17: Save register group for flags (3)

100: system bus interface control unit

103: fixed disk controller 104: machine control unit

The present invention relates to an information processing system having an information storage device such as a personal computer, a workstation, an office computer, and an external storage device.

As a control method of an external storage device in a conventional information processing system, for example, a technique as described in Japanese Patent Laid-Open No. 57-86910 is common.

Here, the structure of such a conventional conventional information processing system is shown in FIG.

In FIG. 5, (1) is an MPU, (2) is a temporal register group, (3) is a lag inside the MPU (1), (4) is a microprogram counter, (5) is an incrementer, (6) microprogram dress, (7) MPU (1) internal bus, (8) microprogram memory, (9) main memory (main memory), (10) disk controller, (11) A disk drive, l2 is a program memory for disk control, 13 is a memory bus, 14 is a system bus 3, and a microprocessor for controlling the disk control unit.

6 shows the disk control unit 10 in detail.

In the drawing, reference numeral 100 denotes a system bus interface controller, 101 a disk cache memory, 102 a read / write control unit for controlling read and write of a disk drive, 103 a fixed disk controller, Machine control unit 105 is an interrupt signal for the microprocessor 30 in the system bus interface control unit l00, 106 is an interrupt signal generated for the microprocessor 30 in the fixed disk controller 103, (107) ) Is an interrupt signal generated by the machine control unit 104 to the microprocessor 30, 108 is a control signal between the read / write control unit 102 and the fixed disk controller 103, and 109 is a fixed disk controller (10) The internal control signal and control bus are shown. (110). Reference numeral 111 denotes a data bus, 112 denotes a control program memory, 113 denotes a control signal between the read / write control unit 102 and the disk drive 11, 114 denotes a machine control unit 104 and a disk drive ( 11) Control signal between.

As described above, the conventional information processing system has a configuration in which each of the central processing unit and the fixed disk unit has a microprocessor. In addition, the interrupt processing of the MPU 1 on the central processing unit side receives and processes interrupts for each paragraph of the machine language instruction.

Here, the operation of the disk control unit 10 in the case of executing processing such as logical address / modal address conversion or command interpretation will be described.

In this case, an interrupt signal is output to the microprocessor 30 from the system bus interface controller, the fixed disk controller, or the machine controller, which is a source of processing.

The interrupted microprocessor 30 executes the control in accordance with the contents of the program memory 12 for disk control in accordance with the respective processing contents and executes the processing.

In the control technology of the fixed disk device shown in the prior art, there is a problem in that an LSI part having a function of a microprocessor is required for the fixed disk device control, which hinders miniaturization due to the reduction of the number of internal parts.

It is an object of the present invention to provide a technique for miniaturizing an information processing system by reducing the number of built-in parts for controlling an external storage device while maintaining conventional system performance.

In order to achieve the above object, the present invention provides a microprocessor that is controlled by a microprogramming scheme and that can accept interrupt requests for each paragraph of a microinstruction. The present invention provides a microprocessor having a save circuit for saving the contents of all registers to a save register, such as a used register register or a flag storing flag.

According to the microprocessor according to the present invention, the interrupt request is received each time the microinstruction finishes executing, and the contents of all the registers used for executing the microinstruction inside the microprocessor are saved in the save register. Therefore, subsequent interrupt processing can use all resources in the microprocessor, including the operation unit.

Therefore, by using the microprocessor according to the present invention, whenever the micro-instruction is finished, the interrupt request from the external storage device such as a fixed disk device can be accepted, and the external storage device can be controlled by the responsive interrupt processing. A microprocessor provided in a conventional external memory device while maintaining the conventional system performance; It is possible to reduce the number of LSI parts with the ability to reduce the size of the device.

An embodiment of an information processing system according to the present invention will be described below.

1 shows the configuration of an information processing system according to the present embodiment. In the drawing, 1 is an MPU. In the present embodiment, as the MPU 1, a microprocessor interrupted at every microinstruction, that is, at the micro level, is used. As the microprocessor interrupted at such a micro level, those disclosed in Japanese Patent Laid-Open No. 61-115133 are known.

In the MPU 1, (2) is a temporary register group in the MPU (1) temporarily used for execution of micro instructions for realizing machine language instructions, and (3) is temporarily used for execution of micro instructions. The status flags inside the MPU (1), (4) the microprogram counter specifying the address of the microprogram to execute, (5) the incrementer for updating the microprogram counter, (6) the microprogram address (7) is an internal bus of the MPU 1, (8) is a microprogram memory for storing microprograms, (12) is a program memory for disk control, and (18) is a microprogram level interrupt. The microstill address 19, which is the jump destination address of the microprogram, is a selector. In addition, in FIG. 1, only a characteristic part is shown in this Example, and the site | parts, such as the calculation part which performs the structure and function similar to the conventional one, are abbreviate | omitted.

In the present embodiment, particularly, the save register group 16 for the temporal register group 2 and the save register group l7 for the flags 3 are provided in the MPU 1.

9 denotes a main memory device (main memory), 10 denotes a disk controller for controlling a fixed disk which is an external memory device, 11 denotes a disk drive, 13 denotes a memory bus for main memory access, 14 Is a system bus and 15 is a microsteel request signal for requesting an interrupt at the microprogram level.

Next, the configuration of the disc control section 10 is shown in FIG.

In the drawing, reference numeral 100 denotes a system bus interface controller, 101 a disk cache memory, 102 a read / write controller for controlling reads and writes to a disk drive, 103 a fixed disk controller, and Machine control unit 105 is the interrupt signal generated by the system bus interface control unit 100, 106 is the interrupt signal generated by the fixed disk controller 103, 107 is the interrupt signal generated by the machine control unit 104 115 denotes a logic gate for outputting the logical sum of three interrupt signals as the microsteel request signal 15, 108 denotes a control signal between the read / write control unit 102 and the fixed disk controller 103, Denotes a control signal and a control bus inside the fixed disk control unit 10. Reference numerals 110 and 111 denote data buses, 113 denote control signals between the read / write control unit 102 and the disc drive 11, and 114 denote between the machine control unit 104 and the disc drive 11, respectively. The control signal is shown.

In the present embodiment, the microprocessor of the central processing unit executes the control which the microprocessor in the conventional fixed disk apparatus is in charge of in order to reduce the number of internal parts and to miniaturize the apparatus itself.

The operation will be described below.

In the case where the fixed disk device executes processing such as logical address / modal address conversion and command interpretation, first, the request for interrupt processing from the system bus interface controller, the fixed disk controller, or the machine controller, which is the request source for processing, requests the micro-steel request signal ( 15) to the MPU 1.

In addition, in the present embodiment, the microsteel request signal 15 is applied to the interrupt signal 105 for the microprocessor 30 by the system bus interface controller 100 and the microprocessor 30 for the fixed disk controller 103. Although the interrupt signal 106 and the machine control unit 104 output the logical sum of the interrupt signals 107 to the microprocessor 30, the three interrupt signals may be treated as individual micro steel request signals.

By the way, the MPU 1 having received the micro level interrupt executes control in accordance with the contents of the disk control program 12 stored in the microprogram memory 8 in accordance with the respective processing contents.

Here, FIG. 3 shows the difference between the interrupt processing (microsteel processing) and the normal interrupt processing accepted for each paragraph of the micro instruction.

As shown in the drawing, the normal interrupt processing is executed for each paragraph of the machine unit, and the macrosteel process is received for each paragraph of the micro-instruction.

In this way, the disk control is executed by microsteel processing. For example, even if the machine language executed at the time of interruption requires a long time to execute a multiload instruction, a multistore instruction, a branch instruction, etc. Since the LSI having the microprocessor function provided in the fixed disk device can be removed, the system performance is not deteriorated with respect to the control of the fixed disk device.

Herein, the MPU 1 includes a system bus interface controller 100, a disk cache memory 101, a read / write controller 102 for a disk drive, a fixed disk controller 103, and a machine controller within the disk controller 10. The 104 is configured as an I / O (input and output device) which can be accessed via the system bus 14 or the system bus 14 and the system bus interface control unit 100, respectively (see FIG. 2).

Therefore, the microprocessor in the fixed disk device can be replaced by the microprocessor in the central processing unit by the above processing, and the microprocessor can be executed in a highly responsive microsteel process as described above. Therefore, conventional functions are not lost. .

Next, the interrupt processing of the micro level in the MPU 1 will be described in detail.

The selector 19, which has received the microsteel request signal 15, which is an interrupt request that can be accepted for each micro instruction paragraph in the MPU 1, is stored in the microsteel address 18, i.e., the microlevel interrupt processing program. The leap destination address is output as the microprogram address 6. This transfers the control to the interrupt processing after the time.

At the same time, the temporal register group 2 inside the MPU 1 temporarily used by micro instructions for executing machine language instructions and the MPU 1 temporarily used by micro instructions for executing machine instruction instructions. The internal state flags (3) are automatically stored in hardware in the save register group (16) and (17), respectively.

This is to return to the processing that was executed just before the interrupt processing after the interrupt processing.

At the end of interrupt processing, the control returns to the hardware to its original state.

In this way, the register save and return of the internal state of the MPU 1 in accordance with the micro-steel are executed automatically by hardware, so that a responsive interrupt function can be realized.

As described above, save registers (2) and state flags (3) are stored according to microsteels so that interrupts can be accepted during execution of any machine language instruction. In addition, all resources in the MPU 1 can be used.

Here, the temporal register group 2 inside the MPU 1 and the state flag 3 in the MPU 1 temporarily used by the micro-instruction for executing a machine language instruction are stored in the save register group 16. The save and return processing will be described.

Fig. 4 (a) shows the structure of this save and return mechanism, and Fig. 4 (b) shows its operation timing.

In Fig. 4 (a), registers (3a) are used to execute microinstructions, save registers (17a) are used to save these registers, and (45) and (46) are selectors.

In the normal operation, the selector 45 selects and outputs the normal data 40 and the selector 46 selects and outputs the normal clock 41.

Therefore, the register 3a latches the normal data 40 with the normal clock 41.

At the time of micro-request, the save register 17a latches the contents of the register 3a by latching the output of the register 3a with the clock shown in 42 in FIG.

On the other hand, after the microstill process, the selector 46 selects and outputs the clock shown in 42 in FIG. 4B, and the selector 46 selects the clock shown in 42 in FIG. 4B. The selector 45 selects and outputs the contents of the save register 17a to return the data saved in the save register 17a to the register 3a.

In addition, although one embodiment of the information processing system according to the present invention has been described as an example of an information processing system having a fixed disk device as an external storage device, the external storage device may be a floppy disk device, an optical disk device, or a magnetic tape device. The same kind of storage device can be implemented.

As described above, according to the present embodiment, a short circuit of a microprogram with good responsiveness to a microprocessor is used to perform processing such as logical address / modal address conversion and interpretation of instructions which are conventionally executed by an LSI having a microprocessor function in a fixed disk device. Each interrupt can be executed.

Therefore, it is not necessary to provide LSl having the function of a microprocessor inside the fixed disk device, and the device can be miniaturized by reducing the number of internal parts.

As described above, according to the information processing system of the present invention, it is possible to reduce the size of the information processing system by reducing the number of built-in parts for controlling the external storage device while maintaining the conventional system performance.

Claims (5)

A microprocessor having a control unit for executing a microprogram consisting of a register and a microinstruction using the register, and having a function of accepting an interrupt request at the end of execution of each microinstruction, the save register and the interrupt request. And a save means for saving the contents of all registers used for execution of the microinstruction by the control part to the save register upon receipt. A microprocessor and an external storage device according to claim 1, wherein the microprocessor executes a control process of the external storage device as an interrupt processing when receiving an interrupt request generated from the external storage device. system. The information processing system according to claim 2, wherein the external storage device is a fixed disk device. The microprocessor of claim 2, wherein the microprocessor includes a microprogram memory for storing a plurality of microprograms including a microprogram for controlling the external memory device, and the microprogram as a control process of the external memory device. An information processing system for executing a control microprogram of the external storage device stored in a memory. The fixed disk device according to claim 3, wherein the fixed disk device comprises a system bus interface controller for controlling an interface between a fixed disk drive, a fixed disk internal bus, and a process bus of the microprocessor, and a fixed disk for processing the storage data system. The controller and the machine control unit for controlling the machine of the fixed disk drive, the interrupt request generated from the external storage device is an interrupt request generated from the system bus interface control unit, fixed disk controller or machine control unit, the microprocessor The control program of the external storage device executed by the interrupt processing in the above is an information processing system which is an arithmetic processing program for logical address / various address conversion, command interpretation, and machine control.