JPS59135525A - Loading system of initializing program - Google Patents

Abstract

PURPOSE:To exclude the hardware for loading an initializing program by providing an initializing program loading (IPL) routine including a loading microinstruction group having the initializing program in the form of split immediate data. CONSTITUTION:An IPL routine 103, i.e., a microprogram is equal to a microprogram including a load microinstruction group having an initializing program in the form of split immediate data for each 8 bits for example. This microprogram is started when a power supply is applied. The microinstructions forming the routine 103 include an immediate loading microinstruction (a), an immediate logical shift microinstruction (b), an OR microinstruction (c) and an ADD microinstruction (d).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram-controlled information processing device, and more particularly to an initialization zologram loading method for loading an initialization program into a main memory when power is turned on.

[Technical background of the invention]

This type of information processing device generally uses a ROM I in which an initialization program is fixedly stored, as shown in FIG.
An initialization program loader (hereinafter referred to as IPL) 12 equipped with an IPL is connected to an input/output bus 13 as one of the input/output devices.
It is connected to the.

Loading of the initialization program from the IPL 12 to the main memory (hereinafter referred to as MM) 14 is performed as follows. First, when the power is turned on, a specific address in the control memory 15 where various microprograms are stored is designated, and an initialization program loading routine (hereinafter referred to as IPL routine) is activated. The microprocessor 16 executes the IPL routine, and the IPL1
The second device address and address signal are sent to the data line J7 and control line 18 of the input/output path 13, respectively. The IPL 12 has a device address detection circuit 19.
is provided, and the device address detection circuit 9 detects whether the device address transferred from the micro processor 16 matches its own address and address. When a match is detected, the command register 20
is valid, then a command indicating initialization program loading transferred from the microprocessor 16 is set in the command register 20 in response to the command signal.

As a result, address counter 2, which specifies the address of ROM II, is reset. Next, a read command is transferred from the microprocessor 16 together with the -F signal. This read command P is set in the command register 20. As a result, the output f-to-2j is opened and the program read from the address location of the ROM J1 designated by the address counter 2 is sent onto the input/output path 13 (the data line 17 thereof). Further, the address counter 2 is counted up at a predetermined timing to designate the next address. The microprocessor 16 transfers the program on the input/output path 13 to the MM 14 via the memory path 23, thereby loading the initialization program.

[Problems with background technology]

In this way, the conventional method requires an input/output bus interface no matter how small the IPL, and in addition to the ROM in which the initialization program is fixedly stored, the device address detection circuit, the command register, and the address for the ROM are required. There was a drawback that various types of -Pware such as counters and output r-ts were required.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide an initialization program loading method that does not require the use of special hardware for loading the initialization program.

[Summary of the invention]

In the present invention, the IPL routine (initialization program loading routine) for loading the initialization program into the MM (main memory) is in the form of a microprogram including a load microinstruction group that divides and owns the initialization program as immediate data. A stored control memory is provided, and in the IPL routine, the immediate data in the load microinstruction is low-Peded to a register specified by the instruction, and the contents of the register are directly or indirectly transferred to the MM. By writing the initialization program into the MM, the initialization program divided and arranged as an immediate release during the IPL routine is loaded into the MM. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows the configuration of a microprogram control type information processing apparatus to which the present invention is applied, and 101 is a microprocessor.

102 is an RO in which various microprograms are stored.
A control memory 103 having an M configuration is an IPL routine that is one of the microprograms.

This IPL routine 103 is a microprogram including an initialization program and a group of load microinstructions divided and owned in 8-bit units, for example, as immediate data, and is completely different from the IPL routine shown in the conventional example. However, it is the same as the conventional example in that it is activated when the power is turned on. 104 is a ROM address line from which the address (microprogram address, ROM address) for the control memory 102 is guided from the microprocessor 10, and 105 is a 20-bit ROM, for example, which guides the microinstruction read from the control memory 102 to the microprocessor 10. It is a data line. 106 is a MM (main memory) in which various programs, data, etc. are stored; 107
is a memory path that connects the microphone processor 10 and the MM 106, etc. The data line of memory path 107 is, for example, 16 bits (2 bytes).

FIG. 3 shows the format of various microinstructions constituting the IPL routine 103. (,) is an immediate load microinstruction, (b) is an immediate logical shift microinstruction, and (c) is an OR microinstruction. , (d) is the format of the ADD microinstruction. In the figure, L, GLI.

OR and ADD are symbolic representations of the contents of the op field (operation field, function field) of each of these microinstructions (a) to (d). Further, D indicates a destination register, S indicates a source register, and ■ indicates immediate data. Furthermore, E is an extension section, which is a field in which functions such as MW (memory write) can be specified. Note that if each of the microinstructions (a) to (d) above is expressed in the form of a symbolic instruction (-monomonic), the immediate microinstruction is L D, I
Then, the ξ-dietological shift microinstruction becomes GLID,I. The number in this GLI microinstruction indicates the number of shifts.

Further, the OR micro-instruction becomes OD, I, and the p, Ann micro-instruction becomes AD, I. Furthermore, when MW (memory write) is specified in the extension E in the OR microinstruction, it is expressed as OD, I, MW.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart of FIG. First, when the power is turned on, the microprocessor 101 executes the I/O stored in the control memory 102.
The ROM address indicating the start address of the PL routine 103 is sent to the control memory 10 via the ROM address line 104.
Output to 2. As a result, 51 microinstructions of J71PL Kenno θ3 are transferred from the control memory 102 to the microprocessor 1.
0, and the IPL routine ios is started as shown in the flowchart of FIG. This IPL
In the routine 103, the 1f-r microprocessor 101
PSW (Program 5 status)
A process (step S7) is performed to set the nologram status corresponding to the initialization program in the initialization program. Next, a process (step S2) is performed in which a program start address of the initialization program is set in a location counter (hereinafter referred to as LOC) not shown in the microprocessor 10. Then, the process of writing the initialization program from the address position of MMJO 6 corresponding to this program start address is performed in the following procedure. First, a process (step S3) is performed in which the program start address is set in a memory address register (hereinafter referred to as MAR) not shown in the microprocessor 10. Next, MM1'0 indicated by MAR
The initialization program to be written to address location No. 6 is set in a memory data register (hereinafter referred to as MDR) not shown in the microprocessor 10, and then
A process (step 84) is performed to write the contents of the DH to the address location of the MM 106 indicated by the MAR. Subsequently, processing for updating the contents of the MAR (step 85) is performed. In this embodiment, data writing to MM No. 06 is performed in units of 2 bytes (16 bits), so the contents of MAR are incremented by 2 in Stella 7'S5. Thereafter, step S4. By repeating S5, 9, MM1
An initialization program divided and arranged as immediate data in the (immediate) load microinstruction group of the engineering PL routine 103 is loaded into a predetermined area starting from the program start address of 06.

Next, execution of the above-mentioned IPL routine ios will be explained in detail with reference to the microprogram examples shown in FIGS. 5 and 6. FIG. 5 is an example of a microprogram for setting data in the PSW, LOC, and MAR inside the microprocessor 101, and steps S1.
This corresponds to 82.83. As is clear from Figure 5, this microprogram consists of L microinstructions and G
It consists of four microinstructions: LI microinstruction, L microinstruction, and OR microinstruction.

First, when the preceding L microinstruction is read from the control memory 102, the microprocessor 10 writes an 8-bit I to the DJ register (register specified by the D field).
1 data (data specified by F-field) is set. Here, the DJ register is PSW in the case of step S.
Yes, for Stella fs2, use LOC, step S
3 is preprogrammed to be MAR. Similarly, the work 1 data is the 7'' program status, program start address, and the upper 8 bits of the program start address.

When the L microinstruction is executed, the GLI microinstruction is read. GLI with 10 microprocessors
The microinstruction shifts the contents of the DI register to the left by 8 bits. Next, when the subsequent L microinstruction is read, the microprocessor 10 uses this L microinstruction to transfer 8-bit work2 data (data specified by E field) to the p and D2 registers (registers specified by the D field). ). Here, the D2 register is one of the working registers (not shown) inside the microprocessor 101, for example. The I2 data includes a program status, a program start address, and the remaining (lower) 8 bits of the program start address. When the following L microinstruction above is executed, OR
A microinstruction is read. Microprocessor No.
is the D register (register specified by the D field)
The data that is a combination of the contents of the register D2 and the contents of the D2 register (register specified by the S field), that is, the 16-bit data that is a combination of the data 1 and the data I2, is DI.
Set in register. In this way, by executing the microprogram shown in FIG. 5, the program status is set in Psw, the program start address is set in LOG, and the zologram start address is also set in MAR. . Note that if the system has a system where the data length that can be specified by the field in the microinstruction matches the data length of the data to be set, it is of course possible to set data in PSW, LOC, and MAR with just one L microinstruction. It is. Also, for example, 3
When setting 2-bit (64-bit) data, repeat the above-mentioned L microinstruction and GLI microinstruction to set 24-bit (58-bit) data, and then set the following L microinstruction described above. It is sufficient to execute the microinstruction and the O microinstruction.

Figure 6 shows that data is set in the MDR inside the microprocessor 10, the contents of the MDR are written to MMj06 (corresponding to Stella 7°S4 in Figure 4), and then MAR
This is an example of a micronogram sentence that does not update (+2) the contents of (corresponds to Stella fS5 in FIG. 4). This microprogram consists of a microprogram (4 microinstructions: L microinstruction, GLI microinstruction, L microinstruction, and OR microinstruction) similar to the microprogram in FIG. 5 described above, and an ADD microinstruction. . As is clear, the register designated by the D field of the preceding L microinstruction, GLI microinstruction, and -OR microinstruction in FIG. 6 must be MDR. Further, 11.12 data are the upper 8 bits and lower 8 bits of the initialization program written to the MMJO6 in one data transfer. O in Figure 6
The R microinstruction is characterized by 3 if the extension E specifies MW (memory write). When this OR microinstruction is executed, the above-mentioned PSW, LOC, MAR
As in the case of setting data to , 16-bit data (initialization program) that is a combination of I1 data and I2 data is set to MDR, and then the contents of MDH are set to MA.
It is written to the address location of MM 106 designated by R. Then, when the MW specified OR microinstruction is executed, the ADD microinstruction is read. MAR is specified in the D field of this ADD microinstruction. Furthermore, "2" is set for F yield.

Therefore, the ADD microinstruction adds 2 to j5 and MAR, and sets the addition result MAR+2 to MAR (step 85 in FIG. 4). In other words, the contents of MAR are stored in the next initialization program (16
bit) is updated to the address within the MM 106 to which it should be written. Note that if the system is such that the data length that can be specified by the field in the microinstruction matches the data length written to the MM 106, writing the initialization program to the MM 106 can be done using the L microinstruction that sets the initialization program in the MDR. It is only necessary to use a command-type instruction that specifies incrementing the contents of MAR, and a command-type instruction that specifies MW in its extension E.

〔Effect of the invention〕

As described in detail above, according to the present invention, by providing the control memory with an IPL routine including a load microinstruction group that divides and owns the initialization program as immediate data, a special - It is possible to eliminate the need for software.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the format of microinstructions applied in the above embodiment, and Fig. 4. is a flowchart to explain the operation, and FIGS. 5 and 6 are micro! diagrams related to the above flowchart.
FIG. 3 is a diagram showing an example of a loader ram. 101...Microprocessor, 102...Control memory, 103...IPL (Initialization program loading) routine, 106...Main memory (MM).

Claims (1)

[Claims] In an information processing device using a microprogram control method,
a control memory in which various microprograms including an initialization program loading routine having a group of load microinstructions that divide and own the initialization program as instant data are stored, and the initialization program loading routine is activated when the power is turned on; In the initialization program loading routine, the immediate data in the load microinstruction is loaded into the register specified by the instruction, and the contents of the register are directly or indirectly transferred to the main memory and written into the main memory. an initialization program loading method, comprising: means for loading an initialization program placed in the initialization program loading routine into the main storage device.