JP3047534B2 - Low power consumption system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption system, and more particularly, to a CP such as a personal computer, a word processor, a DTP (Desktop Publishing).
The present invention relates to a low power consumption system that reduces the power of various electronic devices including a U (central processing unit).

[0002]

2. Description of the Related Art In a conventional system using a CPU, in particular, a system using a battery as a main power source, some devices have been devised to reduce power consumption. That is, the power consumption is reduced by monitoring the operation of the units constituting the system and stopping the power supply to the units that have not been operated for a certain period of time. For example, when a floppy disk, a printer or the like is not used, the power supply is stopped. Further, as a method for further reducing power consumption, a method has been considered in which the operation speed is reduced when the unit is operating as hardware but not as software. For example, when the software enters an event waiting state, such as waiting for a keyboard input, the operation speed of the CPU is reduced.

[0003]

As described above, the conventional low power consumption system is premised on detecting a state in which it is not operating as software. But,
In reality, it was difficult to completely detect the state with the system. That is, in the event waiting state, there are a case where the system (OS or BIOS) waits for an event and a case where the application waits for an event. The former can detect the event waiting state in the system. In the latter case, it could not be detected. Therefore, in the conventional low power consumption system, since the operation of the CPU is reduced only when the system waits for an event, the power cannot always be sufficiently reduced. Therefore, an object of the present invention is to provide a low power consumption system capable of detecting an event waiting state in a system and reducing power consumption even when an application waits for an event.

[0004]

[Means for Solving the Problems] In order to achieve the above object,
Because, the power consumption system of the present invention, the reduction of the power consumption of the devices that perform computer processing example Bei <br/> the (1) CP U,
System program side and application program side
Event waiting state detected by CPU
A power consumption system carried out by bringing Gensa,
During the operation of the application program,
Generate interrupt signals at set time intervals and
Interrupt means for periodically starting the
Stem program to application program
To detect the data area in the provided memory space
And the application in the interrupt handling task of the system.
At predetermined time intervals by the
Detects the number of times data has been written to the data area and
If the number of readings is less than a predetermined value, this application
Determines that the application program is waiting for an event
And processing means. Also, (2) above
Serial in the power consumption system described in (1), means for detecting the data area, to interrupt generation by an interrupt means
Note to seek the minimum value of the stack pointer register of Namatoki
Address of the boundary between the data area and the stack area in the storage space
And means for detecting less, and detects the data <br/> data area based on this address.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a low power consumption system according to the present invention will be described below in detail with reference to FIGS. FIG. 1 shows a configuration of a low power consumption system. As shown in FIG. 1, the low power consumption system includes a CPU (Central Processing Unit) that performs various controls, and is connected to the following units.

Clock 2: Generates a clock that is a basic operation of CPU 1. Bus controller 3: controls a bus that connects the CPU 1 to each unit. Memory Management Unit 4: ROM performed (read only memory) 5 and RAM control (random access memory) 6, when a write operation to the address space of the range specified by the CPU1 is performed This is notified to the CPU 1. ROM5
The system stores a system program, character fonts, fixed data such as a Japanese dictionary, etc., and the RAM 6 stores variable data, programs read from an external storage device, and the like. LCD controller 7: The data content stored in the video RAM 8 is displayed on an LCD (liquid crystal display) 9 as a display device in accordance with an instruction from the CPU 1.

FIG. 2 shows an image of each of these memories, ROM 5, RAM 6, and video RAM 8. In the system data area, as shown in FIG. 3, a first area 21 for storing an application start address, a second area 22 for storing a minimum value of a "stack pointer" register, and a third area 21 for storing the number of times a timer interrupt occurs. An area 23 and a fourth area 24 for storing the number of times of writing to the designated address space are provided.

An I / O controller 10 is disposed between the CPU 1 and each of the following input / output devices, and controls each input / output device. Repeat timer 11: Notifies CPU1 of a time interval specified by CPU1. Keyboard controller 12: detects a pressed key of keyboard 13 on which various input keys are arranged, and
Notify 1. Serial controller 14: A controller for controlling serial input / output, and a serial mouse 15 as an input device.
Input control of the data input from is performed. Parallel controller 16: controller for controlling the parallel input output, parallel printer 1 which is an output device
7, the output of the data to be output is controlled. Floppy disk controller 18: Controls a floppy disk drive 19 which is an external storage device.

Next, according to the present embodiment, the system program
The principle on which the system can detect the event waiting state on the application program side will be described. FIG. 4 shows an operation start state of the system program. The application program is read from the external storage device into the RAM 6 and operates. In a single-task OS, only one task is operating at any time. Therefore, as shown in FIG. 4, the system program operates only when a system call is issued by the application program. In other words, while the application program is waiting for an event, the system program is not running.
The event wait state on the application program cannot be detected.

FIG. 5 shows a state in which a system program is periodically operated by an interrupt mechanism.
As shown in this figure, a general computer system has an interrupt mechanism. For example, a system program can be operated periodically by setting a predetermined value in a repeat timer. In this embodiment, an event waiting state of the application is detected in the timer interrupt processing task of the system. The principle and the state of the application program are as follows. (1) When not in the event waiting state, writing is frequently performed on the data area. (2) In the event waiting state, writing to the stack area may be performed frequently, but almost no writing is performed to the data area. (3) Writing to the code area is rarely performed. Therefore, it is necessary to detect the address of the boundary between the data area and the stack area in the memory space provided to the application by the system. In the present embodiment, the boundary address is assumed by obtaining the minimum value of the "stack pointer" register when the timer interrupt occurs.

Next, the operation of this embodiment will be described with reference to FIG. When the application program is started, the start address of the memory space provided to the application is stored in the first area 21 of the system data shown in FIG.
An end address is set in each of the second areas 22. Further, the third area 23 and the fourth area 24 are set to 0, and the number of timer interrupts and the number of times of writing to the designated address space are set to zero. Then, the repeat timer 11 is started. When a system call occurs The repeat timer 11 is stopped. If the CPU operating speed is low, the normal speed is set. Third region 23,
The fourth area 24 is set to 0. At the end of the system call, the repeat timer 11 is started.

When a timer interrupt occurs If the current value of the “stack pointer” register is smaller than the minimum value of the “stack pointer” register in the second area 22, the data is written to the second area 22. If “1” is added to the value of the third area 23 and the value becomes a specified value, the fact is notified when a write operation is performed on the address space in the range of the first area 21 and the second area 22. The memory management unit 4 is set to perform the operation. Also, the third
If the value of the area 23 is a certain specified value, the value of the fourth area 24 is checked. If the number of times of writing to the specified address space is equal to or less than a certain specified value, the operation speed of the CPU 1 is reduced. The fourth area 24 is set to 0. On the other hand, if the number of times of writing to the designated address space is equal to or more than a predetermined value, the operation speed of the CPU is set to the normal speed.
When writing to the address space in the range of the first area 21 and the second area 22, 1 is added to the value of the fourth area 24.

As described above, the timer interrupt measures the "stack pointer detection time" and the "write count detection time" in addition to the function of allowing the system program to operate periodically even if no system call is issued. Is used to The variable area for that is the third area 23.

[0014]

According to the system of the present invention, since the application program detects that the application program is in the event waiting state by using the timer interrupt and the memory management interrupt, it is possible to incorporate special processing into the application program. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of a low power consumption system of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of a memory of the low power consumption system.

FIG. 3 is a conceptual diagram showing a configuration of a system data area in a memory according to the first embodiment;

FIG. 4 is a state diagram showing an operation start state of a system program.

FIG. 5 is a state diagram showing a state in which a system program is periodically operated by an interrupt mechanism.

FIG. 6 is a state diagram illustrating an operation of detecting an event waiting state.

[Description of Signs] 1 CPU 2 clock 5 ROM 6 RAM 11 timer

Claims (2)

(57) [Claims] Performing computer processing includes a 1. A CP U
Reduce the power consumption of equipment by using the system program side.
Detects event wait state on application program
By reducing the operating speed of the CPU
A power consumption system, during operation of the application program, predetermined
The interrupt signal is generated at the set time interval to
An interrupt means that periodically starts the interrupt processing task
And the above system program
Data area in the memory space provided to the RAM
Means for detecting, and the application in the interrupt processing task of the system.
For the above-mentioned predetermined time by the application program
The number of times data has been written to the data area
If the number of writes is equal to or less than a predetermined value,
Application program is waiting for an event.
Low power consumption system, characterized by chromatic and disconnection processing means. 2. The low power consumption system according to claim 1,
Oite, means for detecting the data area, to said interruption means
Of stack pointer register when interrupt occurs due to
Find the value and stack the data area in the above memory space.
Means for detecting the address of the boundary of the
Detecting the data area based on the address.
That power low-consumption system.