JP3331695B2 - Time synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial applications] To overcome the recent performance limitations of tightly coupled computers, multiple instructions and multiple data types (MIMD type)
Distributed main memory type parallel computers (so-called loosely coupled computers) have entered the stage of practical use. However, in the computer having this configuration, the central processing unit (CP) in each processor element (PE) is used.
U) cannot access global storage (so-called common memory) at high speed.

If a mechanism that can access the global storage at a high speed exists, the mechanism can be used to provide a single time mechanism (hereinafter referred to as TOD) in the parallel computer system.
The clock executed by all the processor elements (PEs) is accessed, or the initial value setting process for the TOD clock performed by each processor element (PE) is performed as described above. The time can be synchronized using global storage, so each processor element
The TOD clock in (PE) can be synchronized with high accuracy.

However, as described above, in the above-mentioned MIMD type distributed main memory type parallel computer, the central processing unit (CPU) in each processor element (PE) uses the global memory.
Since there is no means for accessing the so-called common memory at high speed, each processor element (PE) needs to have the TOD clock. At this time, each processor element
It is necessary to synchronize the TOD clock of (PE) with as high accuracy as possible.

In a large-scale parallel computer system, the configuration of a dynamic processor element (PE) is dynamically changed for maintenance and power saving. Specifically, the processor element (PE) is installed during operation of the system. , Disconnection, and partial power on / off are required. Even in such a case, when a certain processor element (PE) is incorporated,
The TOD clock must be precisely synchronized.

[0005] Each processor element (PE)
In a system having a cache memory, when executing the time synchronization program, for example, at the time of instruction fetch, operand fetch,
When a cache miss occurs, a processing delay occurs, and a delay occurs in the processing for time synchronization.Therefore, in order to perform highly accurate time synchronization, when executing a program for time synchronization, It is necessary to take a measure that does not cause a cache miss in the cache memory.

[0006]

2. Description of the Related Art FIG. 3 is a diagram for explaining a MIMD-type distributed main memory type parallel computer system. FIG. 3 (a) shows an example of the entire configuration, and FIG. Ri Contact <br/> shows the watch, FIG. 4 is a diagram illustrating the time synchronization method of the conventional TOD clock, FIG. 5, FIG. 6 is a diagram illustrating barrier synchronization, 5 FIGS. 6 (a1) and 6 (a2) show examples of a hardware configuration for barrier synchronization. FIGS. 6 (a1) and 6 (a2) show examples of programs for achieving the barrier synchronization. Is shown.

FIG. 3 (a) shows each processor element of the MIMD type distributed main memory parallel computer system (hereinafter, may be referred to as PE (0), (1),...) 1. In addition to the central processing unit (hereinafter referred to as CPU) 10, the cache memory (CA) 11, and the main memory (L-ME) 12,
The main memory (L-ME) 12 in a certain PE (0) 1 through a data communication network between PEs (switch connection network) 3 for performing data communication between (0), (1), A mover (MV) that transfers the data in the other PEs (1), to 1; for example, a direct memory access (DMA) mechanism 13 and a PE (0),
(1), barrier processing unit (B
A) 14 and TOD clock (TO, (T1), ~ 100).

The above TOD clocks (T0),..., 100 indicate a consistent elapsed time in order to display the date and time, and are constituted by, for example, a binary counter having a format shown in FIG. ing. The TOD clock 100 performs a counting operation by a predetermined clock, and is incremented, for example, by adding “1” to a bit 51 of FIG. 3B every second. Also, the value of the TOD clock 100 is SETCLOCK (SCK)
Arbitrary values can be set by instructions.

[0009] For example, as shown in FIG.
In the case of an IMD type distributed main memory parallel computer system, each P
E (0), (1), TOD
Clocks (T0), (T1), to 100 are connected, and a predetermined value is set by the SETCLOCK (SCK) instruction executed by the CPU 10 or referred to by a program executed by the CPU 10 .

Since these TOD clocks (TO), (T1),... 100 have real-time conversion values in a real-time data processing system, all PE (0), (1),. The CPU 10 must have the same value, and a different value may cause a malfunction in the data processing system.

For this reason, for example, when the system is started up, all the PEs (0), (1),... 1 are synchronized in advance by the TOD clocks (T0), (T1),. 0) to PE (n) 1 TOD
Synchronization processing is performed so that clocks (T0) to (Tn) 100 have the same value.

The TOD synchronization setting process is performed, for example, as shown in FIG. First, one PE (0) 1 of the MIMD type distributed main memory type parallel computer system becomes the main, and instructs the other PEs (1) to (n) 1 to start synchronization setting. {See processing step 200 in FIG. 4} At this time, for example, it is assumed that the TOD clock (TO) 100 of PE (0) 1 indicates t seconds. The other PEs (1) to (n) 1 turn on a so-called STOP bit provided in a control register (not shown) in order to initialize the TOD clock 100 according to the above instruction. . << Refer to processing step 201 in FIG. 4 >> Thereafter, as is well known, for example, in order to set t + 1 seconds to its own TOD clock (T1), 100100, a predetermined register is set, and the SETCLOCK (SCK) instruction is executed. Run, each PE
The value of t + 1 seconds is set in the TOD clocks (T1) to (Tn) 100 of (1) to (n) 1, and the TOD clocks (T1) to (Tn) 100 stop counting. << Refer to processing step 202 in FIG. 4 >> Then, only the TOD clock (TO) 100 of the main PE (0) 1 performs the counting operation, and when the TOD clock (TO) 100 carries one digit, that is, , T seconds to t + 1 seconds, the synchronizing signal is sent to the TOD clocks of the other PEs (1) to (n) 1 (T
1) to (Tn) 100, and start the count operation of the other PE (1) to (n) 1 TOD clocks (T1) to (Tn) 100.

Thus, all TOD clocks (TO) to (Tn) 1
00 starts all at once from the value of just t + 1 seconds, and synchronization is established. This synchronization signal is transmitted to each of the PEs (1) to (n) 1 by, for example, a dedicated control line (not shown).
Is transmitted to the TOD clocks (T1) to (Tn) 100.

If the synchronization signal is transmitted via the inter-PE data communication network 3 shown in FIG. 3A, the above-mentioned dedicated control line becomes unnecessary, but the synchronization signal is not transmitted by the inter-PE data communication network 3. Notification takes time, and accurate time synchronization cannot be obtained.

Next, a barrier synchronization mechanism provided in the MIMD type distributed main memory type parallel computer system will be described with reference to FIGS. In the parallel computer, each PE
(0), It is necessary to perform synchronous processing for controlling the progress of the program processing of (1). For this synchronization process,
A special synchronization instruction (barrier synchronization instruction) is embedded in the place where synchronization is required. A location where the synchronization command is embedded is called a synchronization point, and the synchronization command inserted at the synchronization point performs a synchronization operation including two parts.

The first half of the synchronous operation is processing for notifying the other PE 1 that it has arrived at this synchronization point, and the second half of the synchronous operation is performed for all the PEs designated as the PEs performing the synchronous operation. This is a process in which the PE 1 waits until it reaches this synchronization point.

FIGS. 6 (a1) and 6 (a2) show each of PEs (0), (1), and -1.
This shows an example of a barrier synchronization program executed by the CPU 10, in which a synchronization instruction is inserted at a predetermined position in the program as shown.

FIG. 6B shows a time chart of the synchronous operation, in which the PE (1) 1 waits for the synchronous instruction executed by the PE (0) 1 to arrive at the synchronous point. Each PE
(0), (1) An example is shown in which the next instruction is executed synchronously from the time when 1 arrives at the synchronization point.

For such processing, each PE (0), (1),.
A hardware mechanism is required to detect whether 1 has arrived at the synchronization point and to notify each PE (0), (1), to 1 of the detection result.

FIG. 5 shows this hardware mechanism. Each PE (0) to (n) 1 is provided with a synchronous processor selection mask 140 and a synchronous detection circuit 141 as shown. In addition, a synchronization processing network (barrier processing network) 4 is provided outside each of the PEs (0) to (n) 1.

1) First, CPUs (0) to 10 of each PE (0) to 1
Sets the set of PEs (0) to 1 to which the synchronization processing to be applied will be applied using the synchronization processor selection mask 140. The synchronous processor selection mask 140 is composed of a number of latches equal to the number of PE (0) to (n) 1 in the parallel computer system, and each bit corresponds to each PE (0) to (n) 1. are doing. The CPU 10 sets the bit corresponding to PE 1 to be synchronized to “1” and sets the non-corresponding bit to “0”.

2) When the execution of the program executed by each of the CPUs (0) to 10 reaches the synchronization point where the synchronization instruction is inserted, the arrival at the synchronization point is notified to the other PEs (1). ~
The process of informing 10, that is, the first half of the above-mentioned synchronization command is performed. Specifically, “1” is set in the synchronization point arrival indication latch 142 in the barrier processing unit (BA) 14 in each PE (0).
Set.

3) The value “1” of the synchronization point arrival indication latch 142 is notified to the synchronization processing network (barrier processing network) 4. 4) The synchronous processing network (barrier processing network) 4 is all PE (0)
The signals of the above-mentioned synchronization point arrival indication latch 142 from .about.1 are collected and sent back to all the PEs (0) .about.1.

5) The synchronization detection circuit 141 in the barrier processing unit (BA) 14 of each of the PEs (0) to (n) 1 "corresponds to a bit which is" 1 "in the synchronization processor selection mask 140.
The condition that the synchronization point arrival indication latches 142 from PE (0) to (n) 1 are all “1” is checked. If this condition is satisfied, it is determined that the synchronization has been completed and the second half of the synchronization instruction is processed. Is completed, and execution of the next instruction can be started.

6) The synchronization detection circuit 141 informs its own CPU 10 of the completion of the synchronization by sending a synchronization completion signal (SYN
By notifying E), the CPU 10 starts resuming execution of the next instruction.

[0026]

That is, in the conventional parallel computer system, for example, when the entire parallel computer system is reset, the TOD clocks (T0),... It is reset to a specific value, for example, all “0”. In such a time synchronization method, PE (i) 1 is newly added during the operation of the parallel computer system.
At the time of installation, the TOD clock (T
i) There was a problem that 100 could not be synchronized with the time of other PE (0) -1.

When the number of PEs 1 is small, such as a tightly coupled parallel computer, special hardware for time synchronization is used.
For example, a time synchronization mechanism using the above-mentioned global memory (common memory) is provided, and a time synchronization signal generated at a specific timing is transmitted to all the TOD clocks (T0) to 1 (T0) to 1 of PE (0) to 1.
At 00, the time synchronization of the TOD clocks (T0) to 100 can be performed by a predetermined procedure of the time synchronization program distributed at high speed. For example, as in the above-described MIMD type distributed main memory type parallel computer system, When the number of PEs 1 is several tens to several hundreds, there is a problem that accurate time synchronization becomes difficult. This problem is explained by the main PE (0) 1 described in FIG.
The same applies to a time synchronization method using a dedicated line.

Further, the above-mentioned parallel computer system has
In the method of performing time synchronization by executing a program executed by the CPU 10 using the data communication network 4 between PEs, it takes time to perform data communication on the data communication network 4 between PEs.
There is a problem that the synchronization accuracy of the clock (T0) to 100 is poor.

The present invention has been made in view of the above-mentioned conventional drawbacks, and
However, the time synchronization of the TOD clock (Ti) 100 of the incorporated PE (i) can be performed even when dynamically incorporated in a parallel computer, and the time synchronization can be performed with an absolute time.
In addition, the TOD clock must be able to be synchronized with higher accuracy than using the data communication network 4 between PEs provided in the parallel computer system. Furthermore, without the need for special hardware for synchronizing the TOD clock, for example, a dedicated control line for time synchronization, the MIMD type distributed main memory type parallel computer system provides highly accurate time synchronization. Attention is paid to the fact that the MIMD-type distributed main memory type parallel computer system is provided with a barrier synchronization mechanism which is a synchronization mechanism of the program processing. It is another object of the present invention to provide a method for performing time synchronization.

[0030]

FIG. 1 is a diagram schematically showing an embodiment of the present invention. The above problem is solved by a time synchronization method configured as follows.

(1) In the multiprocessor system having the barrier synchronization mechanism 4, the parent processor element PE (0) 1 is the first program for time synchronization.
D Clock (T0) 100 is read and the time of this read reference
Time, that is , the TOD of each other processor element PE (1), ~ 1
Clock (T1), the time (A) to be set to ~ 100
PE (1), to notify the ~ 1 your clause. Using the barrier synchronization mechanism 4, each PE (0), 〜1 waits until the synchronization point indicated by the barrier synchronization instruction, and when it is recognized that synchronization has been achieved between all the PE (0), 11 in, parent PE (0) 1 is, self-tO
D Read the clock (T0) 100, find the difference value (B) between the read time and the above time (A), and
(1), ~ 1 is your TOD clock (T1), ~ 100 above time
Set (A) . In the next program b for time synchronization,
The parent PE (0) 1 sets the value of the above difference (B) to all other PE (1),
, And each PE (0), 11 waits until the synchronization point indicated by the barrier synchronization instruction, and uses all the PE (0), 11 When it is recognized that synchronization has taken place, each PE other than the parent PE (0) 1
(1), - 1 own TOD clock (T1), a value of to 100, the difference
The TOD clock (T1), .about.100 is set by adding the minute value (B).

(2) The above-mentioned barrier synchronization mechanism 4 is provided, and
In a multiprocessor system including the cache memory 11, the program a for time synchronization described in the above item (1) is dry-run once, and all the programs a are stored in the cache memory 11. The program a is re-executed, the program b for time synchronization is dry-run once, and all of the program b is stored in the cache memory 11. Then, the program b is re-executed. It is configured to perform the time synchronization described in the above (1).

(3) The barrier synchronization mechanism 4 is provided, and
In the multiprocessor system having the cache memory 11, the program a and the program b for time synchronization described in the above item (1) are dry-run once, and all of the programs a and b are executed. After storing the data in the cache memory 11, the program a and the program b are re-executed to perform the time synchronization described in the above item (1).

[0034]

According to the time synchronization method of the present invention, the MIMD type distributed main memory parallel computer is provided with a barrier synchronization mechanism for controlling the progress of each of the PEs (0) to (n) 1. Pay attention to This is the first program for time synchronization executed by the CPU (0) 10 of the parent PE (0) 1, and the parent PE (0) 1
D Read the clock (T0) 100 and read this value, that is, each PE (1), ~
1 of TOD clock (T1), time should be set to ~ 100 (A), all of the PE (1), to your Ku notification to ~ 1. Above barrier synchronization mechanism
4, each PE (0), 〜1 waits until the synchronization point indicated by the barrier synchronization instruction, and when it is recognized that synchronization has been established between all PE (0), 11, At the time when the synchronization detection circuit 141 detects that all PE (0), ~ 1 have reached the synchronization point (when the detection signal SYNE is sent)
Then, the parent PE (0), ~ 1 reads the absolute time indicated by its own TOD clock (T0), ~ 100, and calculates the difference from the time (A) notified to the above PE (1), ~ 1. The value (B) is calculated and the other PE (1), ~
1 sets the above time (A) to its own PE (1), ~ 1 TOD clock (T1), ~ 100 . Program b for the next time synchronization, a parent PE (0), and 1 is the calculated difference value (B), all the PE (1), notifies the ~ 1, similarly to the above the barrier Using the synchronization mechanism 4, each PE (0), 11 waits until the synchronization point indicated by the barrier synchronization instruction, and when it recognizes that all the PE (0), 11 have been synchronized, Each non-parent PE
(1), 11 is the time of adding the value of the above difference (B) to the value of its own TOD clock (T1), 100100, and setting it to the TOD clock (T1), 100100. This is to synchronize.

More specifically, the time synchronization program a
The time (A) when the parent PE (0) 1 reads out its TOD clock (T0) 100 is used as the reference time for time synchronization, and
1 is notified using, for example, the data communication network 3 between PEs described above, and a barrier synchronization instruction inserted into the program a executed by the CPU 10 of each of the PEs (0) to 1 reaches the barrier synchronization point. , Waits for the next instruction to execute, and returns to each PE (0),
When synchronization is established between 1 and 1, the parent PE (0) 1 reads the absolute time of reading its own TOD clock (T0) 100 and the above PE (1).
The difference (B) from the synchronization reference time (A) notified to ~ 1 is obtained, and the other PEs (1), ~ 1, for example, execute the above-mentioned parent PE (0) by the next time setting instruction whose execution has been resumed. Time notified from 1
Set (A) to your TOD clock (T1), ~ 100, and start counting from there.

Similarly, the next time synchronization program b
In the parent PE (0), ~ 1, the value of the difference (B) obtained above is
Notify each other PE (1) ~ 1 and CPU 10 of each PE (0) ~ 1
Waits for the execution of the next instruction up to the barrier synchronization point with the barrier synchronization instruction inserted in the program b executed, and when synchronization is established between the PEs (0), to Adds the difference (B) notified from the parent PE (0) 1 to its own TOD clock (T1), ~ 100 by the time setting instruction, and adds the time to its own TOD clock (T1), ~ 100 Set. In this way, the time synchronization between the PEs (0) to 1 of the parallel computer can be accurately obtained.

[Table 1] It is clear by

Next, each PE (0) of the above parallel computer system
1 to 1 have a cache memory (CA) 11, there is a difference in the state of the cache memory (CA) 11 of each PE (0) to 1 due to the difference in the programs executed so far. When the time synchronization programs a and b are executed in (i) to 1, the time synchronization programs a and b
However, if a cache miss occurs because it does not exist in the cache memory (CA) 11, processing delay occurs in the PE (i) -1.

Therefore, according to the present invention, when the time synchronization programs a and b are executed, the time synchronization programs a and b are set so that a cache miss does not occur as described above.
b is executed once (called dry run) so that the time synchronization programs a and b are present in the cache memory (CA) 11 and the time synchronization programs a and b are executed again. Thus, it is possible to eliminate the deviation of the synchronization time due to the cache miss.

In the dry run of the time synchronization programs a and b, both of the time synchronization programs a and b may be dry-run at once, and then the time synchronization programs a and b may be executed again. Needless to say, each may be dry-run and then executed again.

As described above, according to the time synchronization method of the present invention, the time synchronization is performed by using the barrier synchronization mechanism originally provided in the parallel computer system. Therefore, a special hardware mechanism for time synchronization is used. For example, the TOD clock between the processor elements (PEs) can be synchronized with high accuracy without requiring a dedicated control line or a high-speed access mechanism to the global memory.
Also, even when dynamically incorporating a new processor element (PE) into the parallel computer system, the present invention provides
By executing the time synchronization programs a and b including the barrier synchronization instruction, there is an effect that time synchronization can be performed.

[0041]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram schematically showing one embodiment of the present invention, and FIG. 2 is a diagram for explaining a dry run of the time synchronization program of the present invention.

According to the present invention, in a multiprocessor system provided with a barrier synchronization mechanism 4, the parent PE (0) 1 uses its own TOD clock in the first program for time synchronization.
(T0) 100 is read, and this value, that is , each other PE (1), ~ 1
The TOD clock (T1), the time (A) to be set to
E (1) to E (1) are notified, and using the barrier synchronization mechanism 4, each PE (0), to 1 waits until the synchronization point indicated by the barrier synchronization instruction, and all PE (0), to When the parent PE (0) 1 recognizes that synchronization has been established between the two, the parent PE (0) 1 reads the value of its own TOD clock (T0) 100 and calculates the value of the difference from the time (A).
(B) , the other PEs (1), ~ 1 set the time (A) notified from the parent PE (0) 1 to their TOD clock (T1), ~ 100, and synchronize the next time Program b for parent PE (0) 1
Informs all the PEs (1), to 1 of the difference value (B) from the time (A) notified to each of the PEs (1), to 1, and similarly to the above, the barrier synchronization mechanism 4 , Each PE (0) ~ 1 waits until the synchronization point indicated by the barrier synchronization instruction, and
E (0) at the time of the recognition that the synchronization is established between the ~ 1, parent or more
Outer PE (1) ~ 1 is the value of self TOD clock (T1) 100
The means for adding the difference value (B) to set the TOD clock (T1), .about.100, and the means for executing the time synchronization first program, b after dry-run, implements the present invention. It is a necessary means. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the time synchronization method of the present invention will be described with reference to FIGS. 1 and 2 while referring to the bayary synchronization mechanism described with reference to FIGS. First, the time synchronization method according to the present invention is premised on a parallel computer system having a barrier synchronization mechanism. For that purpose, to explain again, the barrier synchronization instruction is inserted at a predetermined position in the program, and in each of the PEs (0) to 1, the barrier synchronization instruction is executed to reach a synchronization point on the program. Have reached that other
A process for notifying PEs (1) to 1 (this process is called the first half of the synchronization process), specifically, a synchronization point arrival indication latch 142
Is set to "1". The value of the synchronization point arrival indication latch 142 is notified to the synchronization processing network (Baari synchronization network) 4, and the synchronization processing network (Baari synchronization network) 4
The signals of the synchronization point arrival indication latches 142 from the PEs (0) to 1 are collected and returned to all the PEs (0) to 1, and the synchronization detection circuit 141 of each of the PEs (0) to 1 outputs the signals to all the PEs (0) to 1. When it is detected that the synchronization point arrival indication latch 142 from “0” to “1” has become “1”, it is determined that the synchronization has been completed and the CPU (0) to
It is necessary to perform the process of notifying 10 (this process is called the second half of the synchronization process). << See FIG. 5 >> The time synchronization according to the present invention uses the above barrier synchronization mechanism. First, when the parallel computer system is powered on, the parent PE (0) 1 is determined, and the parent PE (0) 1 is determined.
(0), ~ 1, etc., the time synchronization program a is executed, and the parent PE (0) 1 reads out its own TOD clock (T0) 10 and writes the time (A) at that time to the data communication network between PEs. (Switch network) 3 through other PE (1) -1
To be notified. << Refer to processing steps 300 and 400 in FIG. 1 >> Next, when the barrier synchronization instruction inserted in the time synchronization program a is executed, a so-called barrier synchronization point {see the operation time chart of FIG. 6B} waits. Each PE
When barrier synchronization is established between (0) and (1), the parent PE (0) 1 calculates the difference B between the time (A) and its own TOD clock (T0), and in each PE (1) to 1, Sets the time (A) notified from the parent PE (0) 1 to its own TOD clock (T1), 〜10. This setting process is performed by the synchronization detection circuit 1 of each PE (1), ~ 1.
The synchronization may be performed by hardware using the synchronization completion signal SYNE from 04, or may be performed by a time setting (SCK) instruction executed next after barrier synchronization is completed. Assuming that the time from the time (A) until the barrier synchronization is obtained is α, the difference B = α. here,
Temporarily terminate the PE synchronization process. << Refer to processing steps 301 and 401 in FIG. 1 >> Next, in the parent PE (0) 1, the time synchronization program b is executed to convert the difference B (= α) into the PE data communication network (switch connection network). ) Notify the program on the other PE (1) ~ 1 via 3).処理 Processing step of Fig. 1 30
2,402} and wait until the so-called barrier synchronization point {see the operation time chart of FIG. 6 (b)}. When barrier synchronization is established between the PEs (0) to 1, the difference B (= α) notified from the parent PE (0) 1 in each of the PEs (1) to 1 is compared with its own TOD clock (T
1) Add ~ 10 and reset. The waiting time from the first barrier synchronization point to the next synchronization point is β. << Refer to processing steps 303 and 403 in FIG. 1 >> When this barrier synchronization is achieved, that is, in the synchronization detection circuit 141 of each PE (0) -1, all PE (0)-(n) 1 have arrived at the synchronization point. At the time of detecting that, the TOD clock (T0) 100 of the parent PE (0) 1 has the time (A) + α as shown in the figure.
+ Β, and in the TOD clocks (T1) to 100 of the other PEs (1) to 1, B (= α) notified from the parent PE (0) 1 at the time (A) + β So that the parent PE (0) 1
Synchronizes with the same time as TOD clock (T0) 100.

Next, each PE (0) ~ of the parallel computer system
When 1 has the cache memory (CA) 11, the time synchronization programs a and b may not exist on the cache memory (CA) 11 depending on the state of the cache memory (CA) 11.

In this case, the time synchronization processing may be delayed. Therefore, in the present invention, before the time synchronization programs a and b are executed, the time synchronization programs a and b are executed empty (dry run) so that the time synchronization programs a and b always exist in the cache memory (CA) 11. After that, the actual time synchronization programs a and b are executed.

FIG. 2 shows an example of the execution form of the dry run in this case. In FIG. 2 (a), each of the two time synchronization programs a and b is independently dry-run, FIG. 2B shows a case where the synchronization programs a and b are executed.
In this example, both the time synchronization programs a and b are executed at the same time after the dry run of both the time synchronization programs a and b are performed at once.

The dry run of the time synchronization programs a and b is a process for ensuring that the time synchronization programs a and b exist in the cache memory (CA) 11. Needless to say, the actual time synchronization programs a and b may be executed.

[0048]

[0049]

As described above in detail, according to the time synchronization method of the present invention, time synchronization is performed using the barrier synchronization mechanism originally provided in the parallel computer system. It does not require a special hardware mechanism such as a dedicated control line or a high-speed access mechanism to the global memory.
The TOD clock between each processor element (PE) can be synchronized. Also, even when a new processor element (PE) is dynamically incorporated in the parallel computer system,
By executing the time synchronization programs a and b including the barrier synchronization instruction according to the present invention, there is an effect that time synchronization can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a dry run of a time synchronization program according to the present invention.

FIG. 3 is a diagram illustrating a MIMD-type distributed main memory parallel computer system.

FIG. 4 is a view for explaining a conventional time synchronization method of a TOD clock.

FIG. 5 is a view for explaining barrier synchronization (part 1);

FIG. 6 is a view for explaining barrier synchronization (part 2);

[Explanation of symbols]

1 Processor element ｛PE (0) to PE (n)｝ 10 Central processing unit (CPU) 11 Cache memory (CA) 12 Main memory (L-ME) 13 Mover
(MV) 14 Barrier processing unit (BA) 100 TOD clock (T0) to (Tn) 2 Global memory (Common memory) 3 Data communication network between PEs (Switch connection network) 4 Barrier processing network, barrier synchronization mechanism 200 to 205,300 to 303,400 to 404 Processing steps a, b Time synchronization program Barrier synchronization instruction, synchronization instruction

Continuation of the front page (56) References JP-A-63-191217 (JP, A) JP-A-3-288956 (JP, A) JP-A-4-277953 (JP, A) (58) Fields studied (Int .Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (1)

(57) [Claims] In 1. A Contact Keru time synchronization method in a multi-processor system with a barrier synchronization mechanism, time synchronization first program for the, parent processor Jer
Instrument reads the self of the clock, the read-out basis
The time to notify all other processor elements, with the barrier synchronizing mechanism, each processor element <br/> waits until the synchronization point barrier synchronization instruction instructs, synchronized among all the processor elements Once it is recognized that the parent processor element of its own clock time and the group
It calculates a difference value of the quasi-time, all of the other processors d
The element sets the above reference time on its own clock, and in the second program for the next time synchronization, the parent processor
The element uses the value of the above difference for all other processors.
Notify the element, with the barrier synchronizing mechanism similar to the above, each processor
The sub-element waits until the synchronization point indicated by the barrier synchronization instruction, and when it recognizes that all the processor elements have been synchronized, each processor element other than the parent processor element
Is a method of adding the value of the above difference to the value of its own clock and setting it as its own time.