JPS63244207A - Pulse measuring instrument - Google Patents

Abstract

PURPOSE:To simplify a capture interruption processing and to execute it at a high speed, and to improve the processing capacity of a central processing unit by allocating two addresses to a capture register, and executing independently an access to the upper and lower bit values. CONSTITUTION:A free running counter 100 counts a count clock phi. An 18 bit capture register 101 inputs and holds a value of the counter 100 by synchronizing with an input timing of an external signal 200. Also, each other address is allocated to the upper 16 bits and the lower 16 bits so that the upper 16 bits and the lower 16 bits can be read out independently, at the time of reading out a value which a central processing unit 010 has inputted. The central processing unit 010 executes an interruption processing for reading a value of the register 101, and in this case, a shifter 104 controls which 16 bits of the upper or the lower ones of the value of the register are to be read out. In such a way, a burden of a software can be reduced b7y eliminating a count clock switching operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse measuring device, and more specifically, to a timer/counter for controlling peripheral devices such as automobile engines and motors.

BACKGROUND OF THE INVENTION Today, microcomputers have become highly integrated due to advances in LSI technology, and various peripheral hardware has come to be mounted on a single chip.

Among such peripheral hardware, the timer/count unit is used to control the period of the reference signal generated by the controlled object when controlling equipment such as automobile engines and motors.
It is essential for measuring the phase, etc., and performing control using the measured values.

A normal pulse measuring device measures the period of a reference signal generated by a controlled object. It is provided with a register (hereinafter referred to as a capture register) that captures and holds the value of the timer in synchronization with the generation timing of the reference signal output by the controlled object.

Normally, when controlling equipment such as automobile engines and motors, the frequency of the pulse signal generated by the controlled object varies over a wide range, so the timer/counter unit described above is used to measure the period and width of the pulse with high precision. It is equipped with a high-frequency count clock and a low-frequency count clock for counting long-cycle measurements, and the count clock can be selected by software to perform counting operations depending on the operating state of the device.

Next, with reference to FIGS. 7, 8, and 9, a conventional technique will be described for the case where the frequency of the reference signal emitted by the control object described above varies over a wide range.

FIG. 7 is a block diagram of a conventional pulse measuring device.

The pulse measuring device 003 includes a central processing unit old 0 that executes programs/calculations, a timer/counter unit 022 that measures the timing of generation of external signals, a memory 040,
Peripheral bus 030 for transferring data between the timer/counter unit, central processing unit, and each peripheral hardware
The timer/counter unit 022 includes a free running counter 110 that receives two different count clocks φΔ and φB, and a capture register 111 that captures the input timing of the external signal 201. The free running counter 110 can select either one of the count clocks φA1φB as the count clock, and after the system is set, the count clock φB is selected as the count clock.

Further, the count clock φA has a higher frequency than the count clock φB. Therefore, after the system is reset, when the free running counter 110 counts φB,
The count period of the free-running counter 110 becomes longer, which can be used when the input frequency of the external reference signal is low. Furthermore, when the count clock φA is set, the count period of the free running counter 110 becomes short, which corresponds to the case where the input frequency of the external reference signal is high and a measurement value with high resolution is required.

Further, in the following, to simplify the explanation, the pit length of the free running counter 110 and the peripheral bus 030 is 1.
This will be explained as 6 bits.

The memory 040 is a data storage area for the central processing unit 010 to measure the input cycle of the external signal 2010 from the value of the capture register 111, and is a capture value storage area 0.
41.042, a periodic data storage area 043, and a count clock switching flag 044 indicating that the interrupt processing count clock has been switched.

Count clock switching flag 04 in memory 040
4 is a software flag to indicate that the central processing unit 010 has switched the count clock of the free-running counter 110 during interrupt processing.If the central processing unit 010 switches the count clock during interrupt processing, the central processing unit 010 switches the count clock. Set the flag to “1”,
Set to “0” if the count clock is not switched.

Next, the case of capturing in synchronization with the external signal 201 will be described with reference to the timing chart of FIG.

After the system is reset, the aforementioned free running counter 110 performs a counting operation every time the count clock φB is input.

The capture register 111 captures and holds the value of the free running counter 110 in synchronization with the timing tl when the external signal 201 becomes active.

Further, at the timing of tl, the central processing unit 010 activates an interrupt process, captures the value of the capture register 111, performs processing to store it in the capture value storage area 041 in the memory 040, and at the same time
The period of external signal 201 is determined from the value of 2, and external signal 20
Control is performed to select the count clock according to the input frequency of 1.

The above operation is the same at the subsequent timings t2, t3 to t12.

The above interrupt processing will be explained below using the flowchart of FIG.

■ Count clock switching flag 044 Determine whether it is "1" or not, and determine whether the count clock was switched from the previous capture to the current capture.

■-1i If the count clock switching flag is 1''' in ■-1i, the count clock has been switched, and the previous capture value is the value captured from the free running counter counting with the count clock before switching. The current capture value is the value captured by the free running counter that is counting with the count clock after the count clock has been switched.

In this case, the input timing interval of the external signal 201 can be obtained by simply subtracting the two captured values, but
Since the count clock is switched during the process, the period of the external signal cannot be obtained.

Therefore, in this case, the cycle is not calculated from the previous capture value, and the value of the capture register 111 is simply stored in the capture value storage area 041 as data for the next capture interrupt, and the count clock switching flag 044"0"' to complete interrupt processing.

In this case, in the interrupt processing, only the count clock switching operation is performed, and period measurement is not performed, so that the control information for the controlled object is subjected to the correction processing intended by the user. For example, a process such as using the previous cycle data as a control parameter is executed.

(2)-1i If the count clock switching flag is "0" in (2), the value of the capture register 110 is stored in the capture value storage area 042.

(2) Next, the value in the capture value storage area 041, which stores the previous capture value, is subtracted from the value in the capture value storage area 042, which stores the current capture value.

■ Store the calculation results in the periodic data storage area 043.

■ Capture the value of capture 111 in storage area 04
Transfer to 1.

■ Determine whether the periodic data is larger than FOOOH.

If the periodic data is larger than FOOOH according to the above judgment, processing is performed to lower the frequency of the count clock so that the periodic data does not overflow. FOOOH the periodic data comparison value for
It will be explained as follows.

■=i If the periodic data is greater than FOOOH, the count clock is switched to φB and the process of ■ is performed.

-1i If the periodic data is smaller than FOOOH, then it is determined whether the periodic data is larger than 0100H.

Similarly to ■, if the periodic data is smaller than 0100 according to the above judgment, processing is performed to increase the frequency of the count clock so that the significant figures of the periodic data do not become small. However, in this explanation, for the sake of simplicity, , hereinafter, the comparison value of periodic data for increasing the frequency of the count clock will be explained as 0100H.

(2) If the -1 period data is greater than 01008, the interrupt processing is completed.

-1i If the period data is smaller than 0100H, switch the count clock to φA.

(2) Set the count clock switching flag 044 to "l" and complete the interrupt processing.

Through the above processing, the timer/counter unit 022 performs a counting operation using a count clock that matches the dynamic range of the input frequency of the external signal 2010, and measures the period of the external signal 201.

Problems to be Solved by the Invention In conventional pulse measuring devices, when the dynamic range of the input frequency of the external reference signal is wide, the count clock input to the counter is switched to ensure resolution of the control value. In order to avoid this, it is necessary to perform software processing such as checking the count clock switching flag, switching the count clock, and correcting processing after switching the count clock, which not only increases the execution time of interrupt processing but also requires external As the reference signal input frequency becomes higher, there is a problem that the execution time of interrupt processing reduces the processing efficiency of the central processing unit, which in turn causes a reduction in the processing efficiency of the entire system.

In addition, conventional pulse measurement devices respond to changes in the input frequency of the external reference signal by switching the count clock, but in the first capture after switching the count clock, the input period of the external signal cannot be calculated. If this becomes impossible and control information is missing, and if the input frequency of the external signal changes so frequently that it becomes necessary to switch the count clock for each capture interrupt, There is a problem in that it becomes completely impossible to calculate the input cycle, making it impossible to control the controlled object.

Therefore, the present invention aims to provide a pulse measuring device that solves the problems of the conventional pulse measuring device described above.

Means for Solving the Problems The pulse measuring device according to the present invention includes a central processing unit, a counter that counts a single count clock, and a register that captures and holds the value of the counter in synchronization with an external signal. and a shifter that shifts the value of the register, the register is made up of a plurality of unit parts starting from different bit positions, different addresses are set to the plurality of unit parts, and the shifter is configured to shift the value of the register. The central processing unit reads out a plurality of unit parts starting from different bit positions of the register independently according to the address designation.

Effects The above-described pulse measuring device according to the present invention stores the value of the counter and assigns multiple addresses to the register to hold it, so when the central processing unit accesses the capture register, the central processing unit can control only one of the values in the capture register. A valid range of data can be obtained by simply reading registers. Therefore, the burden on the software is reduced by eliminating the count clock switching operation, and highly accurate measurement corresponding to changes in the input frequency of the external signal can be performed with a minimum amount of hardware.

Embodiments Hereinafter, embodiments of a pulse measuring device according to the present invention will be described with reference to the accompanying drawings. Note that the following examples are merely illustrative of the pulse measuring device according to the present invention, and the present invention
The present invention is not limited to these examples.

Example 1 Next, a first example of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram of an embodiment of a pulse measuring device according to the present invention. The illustrated pulse measuring device 001 comprises a central processing unit 010, a memory 040, a timer/counter unit 020, and a 16-bit wide peripheral bus 030.

The timer counter unit 020 has a count clock φ
18-bit free running counter 1
00 and an 18-bit capture register 101 that captures and holds the value of the free running counter 100 in response to the input of an external signal 200 generated by the controlled object. The upper 16 bits of the value of
A shifter 104 controls which of the lower 16 bits are read out.

The 18-bit free running counter 100 corresponds to a conventional 16-bit free running counter in which the count clock φB has a period four times that of φA.

That is, the lower 16 bits of the 18 bits in this embodiment correspond to the case where the conventional free running counter counts φA, and the upper 16 bits of the 18 bits correspond to the case where the conventional free running counter counts φA. This corresponds to the case where φB is counted.

In this embodiment, the free running counter 100 and capture register 101 have a bit length of 18 bits, and the peripheral bus 030 has a bit length of 16 bits, but it goes without saying that a similar configuration can be made with bit lengths other than those mentioned above. .

The memory 040 has a capture value storage area 041.0 that stores the values measured by the timer counter unit 020.
42, a periodic data storage area 043 for storing periodic data obtained from the captured values.

Next, the operation of each part of the pulse measuring device 001 will be explained.

The free running counter 100 performs a counting operation every time the count clock φ is input.

The capture register 101 synchronizes with the manual timing of the external signal 200 and controls the free running counter 10.
When reading the value captured by the central processing unit 010 using the 18-bit register that captures and holds a value of 0, the capture is performed so that both the upper 16 bits and lower 16 bits of the 18 bits can be read independently. register 101
Different addresses are assigned to the upper 16 bits and lower 16 bits.

The value of the upper 16 bits of the 18-bit capture register is substantially equal to the value captured by the counter of count clock φ/4. That is, the lower bits of the capture register 101 are equal to the value captured when the counter's count clock is set to φ in the conventional example, and the upper 16 bits of the capture register 101 are equal to the value captured when the counter's count clock in the conventional example is switched to φ/4. equal to the value captured by

When the central processing unit 010 reads out the value of the capture register 101, the shifter 104 changes the bit position of the read data according to different addresses of the upper 16 bits and the lower 16 bits.
If it is a bit address, the value of the upper 16 bits of the 18-bit capture register 101 is transferred to the 16-bit peripheral bus 0.
30, and if the address is the lower 16 bits, it is 18
The value of the lower 16 bits of the bit capture register 101° is output to the 16-bit peripheral bus 030.

Next, the actual operation of the hardware of this embodiment will be explained.

As shown in FIG. 2, the free running counter 100 counts the count clock φ, and the capture register 101 captures the value of the free running counter 100 in synchronization with the timing at which the external signal 200 is input. performs interrupt processing to read the value of the capture register 101.

The interrupt processing performed by the central processing unit 010 will be described below with reference to the flowchart in FIG.

The central processing unit 010 activates the interrupt processing described below every time the external signal 200 is input, transfers the value of the capture register 101 to the memory 040, and calculates the period of the external signal 200 from the previous captured value. The following two processes are performed.

(2) Store the value of the upper 16 bits of the capture register 101 in the capture value storage area 042.

(2) Next, the value in the capture value storage area 041, which stores the previous capture value, is subtracted from the value in the capture value storage area 042, which stores the current capture value.

■ Store the calculation results in the periodic data storage area 043.

(2) Transfer the value in the capture value storage area 042 to the capture value area 041, and store the current capture value in response to the next capture interrupt.

■ Determine whether the cycle data is smaller than 01008. If the periodic data is smaller than 0100H according to the above determination, the lower data of the capture register 101 is read and the periodic calculation is performed again so that the significant figures of the periodic data do not become smaller. Therefore, the comparison value of the periodic data will be explained as 01008 from now on.

(2)-1 If the periodic data is smaller than 01008 in (2) above, read the lower 16 bits of the value of the capture register 101 and perform the process (2).

-1i If the cycle data is greater than 01008, interrupt processing is completed. ' 2 Calculate the captured value storage area 041 from the value in the captured value storage area 042.'

■ Store the calculation results in the periodic data storage area 043,
Complete interrupt processing.

In the above capture interrupt, the period is calculated by reading the value of the upper 16 bits of the capture 101 according to a wide period, and when the input frequency of the external reference signal 200 becomes high and the period data becomes smaller than 01008. To do this, the value of the lower 16 bits of the capture 101 is reread and a cycle calculation is performed.

Through the above processing, the timer/count unit 020 can measure the period of the external signal 200 in accordance with the dynamic range of the input frequency of the external signal 200.

Embodiment 2 Next, a second embodiment of the pulse measuring device according to the present invention will be described with reference to FIG. 4.

In the second embodiment, the phase difference between one reference external signal 200 and two other external signals is determined.

In addition, in FIG. 4, description of the parts already described in Example 1 will be omitted.

The pulse measuring device 003 shown in FIG.
10, memory 040, timer counter unit 021.
It consists of a 16-bit wide peripheral bus 030.

The timer/counter unit 021 is configured by an 18-bit free running counter 100 that counts the count clock φ as shown in FIG. 18-bit capture register 101.1 that captures and holds the value of free running counter 100
02.103 and capture register 101.102
．． When the central processing unit 010 reads the value of 103,
It consists of a shifter 104 that controls which of the upper 16 bits and lower 16 bits of the value of the capture register 101, 102, and 103 is read out.

In the second embodiment, the free-running counter 100 and capture registers 101, 102, and 103 have a bit length of 18 bits, and the peripheral bus 030 has a bit length of 16 bits, but a similar configuration can be used with bit lengths other than the above. Needless to say, it can be done.

The memory 040 has a capture value storage area 041.04 that stores the values measured by the timer counter unit 021.
2. Consists of phase difference data storage areas 045 and 046.

Next, the operation of each part of the pulse measuring device 002 will be explained.

Free running counter 100, capture register 101, shifter 104, central processing unit 010, memory 0
Since 40 is the same hardware as in the first embodiment, a description of its operation will be omitted.

Capture registers 102 and 103 are capture registers similar to capture register 101, and capture external signal 2.
10. The value of the free running counter 100 is taken in and held in synchronization with the input timing of 220.

Similarly to the capture register 101, the capture registers 102 and 103 are used to read and write data to the upper 16 bits and lower 16 bits when the central processing unit old 0 reads and writes.
Different addresses are assigned to the upper 16 bits and the lower 16 bits so that the bits can be accessed independently.

Next, the central processing unit 010 explains the sixth interrupt process for determining the phase difference between the external signal 210 and the external signal 200.
This will be explained with reference to the flowchart shown in the figure.

(2) Store the value of the upper 16 bits of the capture register 101 in the capture value storage area 042.

(2) Store the value of the upper 16 bits of the capture register 102 in the capture value storage area 041.

(2) Subtract the value in the capture value storage area 042 from the value in the capture value storage area 041 to find the phase difference.

(2) Determine whether the phase difference data obtained in (2) is smaller than 01008.

If the phase difference data is smaller than the phase difference data 0100H by the above determination, the lower data of the capture registers 101 and 102 is read and the period calculation is performed again so that the significant figures of the phase difference data do not become smaller, but this will be explained in this embodiment. To simplify the process, from now on, the comparison value of period data will be 0100.
This will be explained as 8.

(2)-1 If the phase difference data is smaller than 01008 in the above (2), the process (2) is performed.

(2)-1i If the phase difference data is greater than 01008, process (2) is performed.

(2) Output the address of the lower 16 bits of the capture register 101, read the value of the lower 16 bits of the capture register 101, and store it in the capture value storage area 042.

(2) Output the address of the lower 16 bits of the capture register 102, read the value of the lower 16 bits of the capture register 102, and store it in the capture value storage area 041.

(2) Subtract the value in the capture value storage area 042 from the value in the capture value storage area 041 to find the phase difference.

(2) Store the calculation result in the phase difference data storage area 045 and end the interrupt processing.

Through the above processing, the timer/counter unit 021 can determine the input timing of the external signal 200 and the input timing of the external signal 210.
External signal 200 and external signal 21 from the input timing of
It is possible to obtain a highly accurate phase difference without depending on the input timing or input frequency of an external signal.

In the above explanation, the case where the phase difference between the external signal 210 and the external signal 200 is calculated is explained.
The phase difference between the external signal 200 and the external signal 200 can also be obtained by similar processing.

Furthermore, in this second embodiment, the case where there are three capture registers has been described, but it is clear that even if the number of capture registers is further increased, the phase difference between multiple signals can be determined by the same processing. .

Effects of the Invention As explained above, in the pulse measuring device according to the present invention, by assigning two addresses to the capture register and providing the function of independently accessing the values of the upper 16 bits/lower 16 bits, the following effects can be achieved. is obtained.

(1) Since the pulse measuring device of the present invention does not perform a count clock switching operation, it is not necessary to determine whether or not the count clock has been switched by interrupt processing using a capture signal, simplifying capture interrupt processing and interrupt processing. It becomes possible to speed up the processing, and improve the processing capacity of the central processing unit.

(2) The pulse measuring device of the present invention does not need to switch the count clock of the internal free running counter by capturing the frequency change of the input pulse.
Periodic calculations can be performed at each capture timing.

(3) Since the pulse measuring device of the present invention can shift the read values of multiple capture registers using a single shifter, when adding capture registers due to an increase in the number of measurement targets, it is possible to shift the read values of multiple capture registers by simply using only the capture registers. It is possible to handle an increase in the number of controlled objects simply by adding more.

As explained above, the pulse measuring device according to the present invention has the following features:
Eliminating the need to switch count clocks reduces the burden on software, allowing highly accurate measurements that respond to changes in the input frequency of external signals with a minimum amount of hardware.

[Main reference number]

001.002.003...Pulse measuring device 010
...Central processing unit 020.021...Pulse measuring device 022 according to the present invention
・・Conventional pulse measuring device 030 ・・Peripheral bus 040 ・・Memory 041.042 ・・Captured value storage area 043 ・・・
Periodic data storage area 044... Count clock switching flag 045.0
46...Phase difference data storage area 100.110...Free running counter 101.102.103.11
1...Capture register 104...Shifter

Claims (1)

[Claims] It comprises at least a central processing unit, a counter that counts a single count clock, a register that captures and holds the value of the counter in synchronization with an external signal, and a shifter that shifts the value of the register, and the register , consisting of a plurality of unit parts starting from different bit positions, and different addresses are set for each of the plurality of unit parts,
The shifter stores the read value from the unit part to the least significant bit, and the central processing unit independently reads out a plurality of unit parts starting from different bit positions of the register according to the address specification. Pulse measuring device.