JPS6358548A - Microprocessor for debug - Google Patents

Abstract

PURPOSE:To simplify the constitution of a back-up device for development of microprocessor by providing an instruction executing part having a function that saves even the contents of a program counter which designates the instruction executed when a debug interruption is produced in a debug interruption mode. CONSTITUTION:An instruction executing part 4 of a debug microprocessor 1 has the microprocessor internal state information (PSW) 4-1 and reads out an instruction via a program (PC) next 4-2 to copy the value of the next 4-2 to a PCcurrent 4-3. Then the processor 1 sets the next 4-1 at the value of the counter to be executed next. The part 4 is informed from a control part 5 that a debug interruption 13 is active and functions to save those information on the PSW 4-1, the next 4-2 and the current 4-3 through a bus control part 2. Thus it is possible to simplify the constitution of a back-up device for development of microprocessor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a debugging microprocessor used in a debugging microprocessor development support device for a system to be debugged. In particular, the present invention relates to a function when the debugging microprocessor transitions from the execution state of a debug target program to the execution of a debug program that displays and changes the contents of memory, registers, etc.

[Conventional technology]

First, an outline of the connection between the microprocessor development support device in which the present debugging microprocessor is used and the debugging target system will be explained with reference to FIG. A microprocessor development support device 27 is connected via a connector 38 and a group 37 in place of the microprocessor installed in the debug target system 39. In addition to the debugging microprocessor l, the microprocessor development support device 27 has a control unit (not directly related to the present invention, so it has been omitted), and a replacement system for the microprocessor to be implemented in the debug target system 39. It has the function of executing the program to be debugged and debugging it. For this reason, the debugging microprocessor 1
Execution of a program in the memory on the debug target system 39 (although it is possible to virtually arrange the memory in the microprocessor development support device 27, this is omitted as it is not directly related to the present invention). , the memory in which the debug program with the debug function is written, which is located in a separate bank in the microprocessor development support device 27, must be executed.

Conventionally, as this type of debugging microprocessor, a microprocessor (hereinafter referred to as the original microprocessor) that should originally be connected to the system 39 to be debugged is used, and its execution is interrupted under certain conditions (hereinafter referred to as a break). In order to transfer control to the debug program on the microprocessor development support device 27, the non-maskable side input (hereinafter NMI) that the original microprocessor has
)'5r: was used to realize a break operation.

FIG. 5 is an internal block diagram of the original microprocessor. The bus control unit 2 controls the address bus 6, data bus 7, and control bus 8, reads instructions, and
Store it in The instruction execution unit 4 internally has a program counter 4-2' (hereinafter also referred to as PC) and microprocessor internal state information 4-1 (hereinafter referred to as program status word: psw). It then receives instructions from the instruction buffer 3 and executes them sequentially. The instruction execution unit sequentially receives the instructions in the program counter 4-2' from the instruction buffer 3, and each time it receives an instruction, the contents of the program counter 4-2' are updated to the value of the next program to be executed. be done. That is, the contents of the program counter 4-2' at the time the instruction is being executed indicates the address of the next instruction to be executed. The instruction buffer control section 11 includes the bus control section 2 and the instruction execution section 4'.
According to the information 10-1.10-2 from the instruction buffer 3
The number of instructions taken into the microprocessor is notified to the outside of the microprocessor through a signal line 12. Also, the interrupt control unit 5
' is an interrupt request from the interrupt terminal (NM114), and the instruction execution unit 4' sends the contents of the program counter 4-2' and the program status word 4-1 to the bus control unit 2.
The command is then saved to memory through the process, and then a predetermined command is executed.

A microprocessor development support device in the case where an original microprocessor that operates in this manner is used as a debugging microprocessor has the configuration shown in FIG. Is the microprocessor development support device 27' the original microprocessor? 1', control unit 19', debug program memo IJ 16, N), 4-engine save memory 17', NM
It is comprised of an I save timing control section 18, a selection circuit 46 that selects the NMI 26 from the system to be debugged and the break request signal 25 from the control section 19'. The break operation that transitions from the execution state of the debug target program 2m to the execution state of the debug program is performed by the microprocessor development support device 27'
Switch to I save memory 17', break request signal 25
The debugging microprocessor 1' (that is, the original microprocessor) stores the saved information (program counter and program status word) in the NMI save memory 17', and then stores the information saved in the debugging program memory 17' in another bank. 16
is given to the original microprocessor 1' and the debug program is started.

The NMI evacuation timing control section 18 and the control section 19' are
The above operations are controlled. Further, the instruction buffer status control unit 44 converts the instruction being executed at the time when the break operation occurs from the instruction buffer control signal 12 and the program counter information saved in the NMI save memory 17', and uses the information to convert the instruction to the control unit 19. It was necessary to have a function to notify ``.

[Problem that the invention seeks to solve]

As mentioned above, when an original microprocessor is used as a debugging microprocessor, because it has an instruction buffer, the time at which the microprocessor reads an instruction and the time at which it executes the instruction are different, and there is a function to adjust this. The microprocessor development support apparatus also requires a selection circuit for selecting the NMI and break request signals from the system to be debugged, which complicates the configuration of the microprocessor development support apparatus.

Means for Solving Problem C] The debugging microprocessor of the present invention is used as a debugging microprocessor for use in a microprocessor development support device, and in addition to the functions of the original microprocessor, the debugging microprocessor of the present invention has the interrupt function of the original microprocessor. It has a debug monthly discount function that has a higher priority than the debug monthly discount function, and in the operation of saving internal information of the debugging microprocessor caused by the opening of the debug phase, execution is executed when the debug monthly discount request processing is completed. In addition to the information on the program counter to be restarted, it also has the function of saving the information on the program counter of the instruction being executed when the Depack monthly interrupt occurred.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a debugging microprocessor showing one embodiment of the present invention. The difference from the original microprocessor shown in FIG. 5 is that the interrupt control section 5 has a debug interrupt 13, and the instruction execution section 4 has a conventional program counter 4-2 (hereinafter referred to as P Cnext).
In addition to the second program counter 4-3 (hereinafter P
This is the point marked with Ccurrent.

When the instruction execution unit reads the instruction using PCnext 4-2, it transfers it to PCcurrent4-3.
4-2 (Copy the D value, then PCnext4-
2 to the value of the program counter to be executed next. That is, PCnext4-2 transmits teno information about the program counter to be executed next to PCcurr.
ent 4-3 will have information about the currently running program counter. In addition, when the instruction execution unit 4 is notified from the interrupt control unit 5 that the debug monthly interrupt 13 has become active, the instruction execution unit 4 sends PSW4-1, PCnext4-2 (PO2-2 in the original microprocessor) through the bus control unit 2. ), P
It has a function to save three pieces of information: Ccurrent 4-3.

FIG. 2 shows a block diagram of a microprocessor development support device using this debugging microprocessor. The difference from the block diagram of the conventional microprocessor development support device 7 is that the instruction buffer status control unit 44 and the interrupts from the system to be debugged and the interrupts from the control unit (
This is because the selection circuit 46 for selecting the break request signal) is eliminated.

A break request signal 25 from the control section 19 is applied to the debug monthly interrupt 13 of the debugging microprocessor. When a break occurs, the control unit 19 causes the break timing control unit 18 to change the memory bank to the break save memory 17 (functionally equivalent to the NMI save memory 17').
Switched to P 5W4-1, P Cnext
4-2, the information of P Ccurrent 4-3 is written to the buffer memory 17, and then the bank is switched to the debug program memory 16, and the debug program runs. At this time, read the program counter information (P
Ccurrent 4-3)” Rake evacuation memory 1
7, the instruction buffer status control unit 4
4 does not need to convert this information. Furthermore, since the debug monthly interrupt 13 is independent of the NMI 14, there is no need to select the NMI 26 from the debug target system 39 and the break request signal 25 from the control unit 19.

Next, other embodiments of the present invention will be described.

FIG. 6 is a configuration diagram of a microprocessor.

Modern microprocessors have complex functions, so they have a control program called a microcode 40 inside the microprocessor 1, 1', and the hardware 42, which is a collection of circuits with simple functions, is controlled by the microcode 40.
It is controlled by the microprocessor to operate it.

In such a microprocessor that performs control using microcode, the NMI function that the microprocessor originally has is constituted by microcode as shown in FIG. When an interrupt is detected, a pointer called a stack pointer (denoted as SP) is used to save the contents of the program status word and program counter to the location pointed to by the pointer. Detect NMI (47
), first SP is incremented (48), and the contents of the program status word are written to the memory pointed to by SP. (49) Next, increment SP by 1 again to 5
0), the contents of the program counter are written there. (
51) Thereafter, the program counter is set to the value of a predetermined entry (52), and control is transferred to the interrupt entry (53). At this time, the operation of the microprocessor development support device using this original microprocessor is similar to that of the microprocessor development support device 27 in the first embodiment.
’ is the same as

FIG. 3 shows the microcode for executing the monthly debugging subscription function in this embodiment. When the monthly debugging interrupt is detected (28), SP is first incremented (29), and the contents of the program status word are written into the SP memory (30). Next, increment SP again to 31X then P C
Write the value of next (32χ Furthermore, increment SP and write the value of PCcurrent there (34).Finally, set the value of the specified entry in the program counter (35X) Transfer control to the interrupt entry (34). 36).

〔Effect of the invention〕

As explained above, the present invention has a debug monthly interrupt, and when the debug monthly interrupt occurs, the psw.

By equipping a microprocessor development support device with a debugging microprocessor that has the function of saving P Cnext and PCcurrent, it is no longer necessary to have an instruction buffer status control unit, a selection circuit for the debug target system and a break request signal, and the microprocessor The development support device can be easily configured.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an embodiment of a debugging microprocessor according to the present invention, FIG. 2 is a functional block diagram of a microprocessor development support device using the debugging microprocessor according to the present invention, and FIG. 3 is a functional block diagram of an embodiment of the debugging microprocessor according to the present invention. Fig. 4 is a connection diagram of the microprocessor development support device and the system to be debugged, Fig. 5 is a functional block diagram of the original microprocessor, and Fig. 6 is the microprocessor realized by microcode. A block diagram of the processor, FIG. 7 is a configuration diagram showing an example of a microprocessor development support device using an original microprocessor, and FIG. 8 is a sequence flow showing the operation of NMI of an original microprocessor realized by microcode. It is a diagram. 1... Microprocessor for debugging, 1'.
...Original microprocessor, 2...
Bus control unit, 3...Instruction buffer, 4...
...Instruction execution unit, 4-1...Program status word, 4-2...Next program counter (PCnext), 4-2'...
Program counter (PC) to be executed next, 4-3.
・・・-・Currently running program counter (P
Ccurrent), 5...Interrupt control unit, 6...Unres bus, 7...Data bus, 8...-ffd[l has, 9... ...Address bus, 9-1゜9-2...Instruction path, 1
0-1.10-2...Instruction buffer control unit input signal, 11...Instruction buffer control unit, 12...
...Instruction buffer control unit output signal, 13...
・Debug monthly interrupt, 14... Non-maskable side interrupt (NMI), 15...-- Interrupt control path, 16... Memory for debug program (debug ), 17...Break save memory, 17'...Nll/II save memory (functionally the same as 17), 18...Break save memory Timing control section, 19.19'...
- Control unit, 20...Debug target program memory, 21-1゜21-2...Buffer, memory selection signal, 22-1゜22-2.22-3...・
・Access signal, 23-1゜23-2...Buffer, 24-1, 24-2...Inverter,
25...Break request signal, 26...
NMI from the debug target system, 27°27'...
...Microprocessor development support device, 28-36
...Debug phase opening processing procedure (processing by microcode), 37... Cable, 38.
... Connector, 39 ... System to be debugged, 40 ... Microcode, 41 ...
... Microphone o-code control path, 42 ... Hardware, 43 ... Microprocessor signal,
44...Instruction buffer status control unit, 45
...Instruction buffer status control unit output signal,
46...Selection circuit, 47-53...N
MI processing procedure (processing by microcode). 'yFJ2 figure ￥J5 figure Foil Otsu figure Cuff figure 26 figure

Claims (1)

[Claims] In a microprocessor that has a function to save the contents of a program counter that specifies instructions to be executed and information representing an internal state to memory, and an interrupt function,
an interrupt control unit having a debugging interrupt function with a higher priority than the interrupt function; and an interrupt control unit having a debugging interrupt function that has a higher priority than the interrupt function; 1. A debugging microprocessor comprising: an instruction execution unit having a function of also saving the contents of a program counter specifying an instruction being executed at the time of occurrence.