JPS61221943A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To grasp easily the executing state of a program and to simplify both debugging and tracing jobs by using a register which saves and stores temporarily the contents of a program counter. CONSTITUTION:The contents of a program saving register (SPC)a12a are first set to an SPCb12b. Then the contents of a program counter (PC)5 are set to a memory address register (MAR)8 as well as to the SPCa12a. The value of the (PC)5 is increased by one and the contents of an address shown by the PC5 are read out and set to an instruction register 6 to be decoded by an instruc tion decoder 6. Then a read-out job if required for the instruction of the next memory address is carried out. When all instruction codes necessary for execu tion of the instruction are read out, the prescribed instruction processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an arithmetic processing device that is provided with means for holding the value of the immediately preceding program counter and that facilitates tracing of, for example, executed blocks.

Summary of the Disclosure" This specification and the drawings describe an arithmetic processing unit that executes processing according to a program, which includes means for temporarily saving and storing the contents of a program counter, so that when the program counter is updated, the current program counter The present invention discloses a technique that allows the current program counter value to be checked against the immediately previous program counter value by saving the contents of the program counter in the storage means and then updating the program counter.

``Conventional technology'' Conventionally, commonly used arithmetic processing units
The PC (hereinafter referred to as PC) is equipped with only one program counter (hereinafter referred to as PC). Therefore, when tracing a program at the time of program depacking, the address of the next instruction to be executed in the program sequence can be found, but the address of the previously executed instruction, that is, the current address (current PC I didn't know the number of PCs before becoming a detective.

[Problems to be Solved by the Invention] A case where the program sequence shown in FIG. WI3 is executed will be explained as an example.

Figure 3: rJMP JIJ command at jt "100" address,
In this example, there is an rJMP JIJ instruction at address "200". Here, if the jump destination Jl" is address "300"', and if we consider when we jump to address '300', the PC value at this time is L300J, but here , from where (from which address) this "300
I have no idea whether it jumped to address ``100''.
``, or jump to address ``300'' following a jump (branch) instruction from address ``200,'' or jump to address ``300'' due to a programming error, etc. by executing an instruction at another address. It is not possible to determine whether the program has been deleted, and it takes a great deal of effort and time to back up and trace the program.

[Means for Solving the Problems] The present invention solves the above-mentioned problems with the following configuration.

That is, a holding means for holding the value of a program counter, and a counter (I) that reads the value of the program counter and stores it in the holding means before updating the program counter.
This can be achieved by an arithmetic processing device equipped with I saving means.

E-effect 1 The execution procedure is sequentially read from the storage means, and when the program counter that performs arithmetic processing etc. is updated, the contents of the program counter are automatically saved to the storage means, and then,
By updating the program counter, it is possible to check the current program counter value and the previous program counter value, making it easier to understand the program execution status and simplifying program depacking, tracing, etc. Become.

[Example" Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which numeral 2 represents an arithmetic logic operation unit and numeral 4 represents a control circuit. The control circuit 4 performs various timing controls, and this timing control may be configured with hardware (logic circuits) or may be configured with a microprogramming configuration. Tamiru can easily respond. Further, 5 is a program counter (hereinafter referred to as PC) that stores the storage location of instructions, 6 is an instruction register, 7 is an instruction decoder that analyzes the instructions in instruction register 6, and 8 is a memory address register (hereinafter referred to as MAR). , 9 is a memory data register (hereinafter referred to as MDR);
10 is an internal bus. Further, 12a and 12b are program counter save registers (hereinafter referred to as SPC) a, b, 1
3 is a memory control circuit, 14 is a memory, and 20 is a general-purpose register, which can be freely read and written by program instructions.

The operation of the apparatus of this embodiment shown in FIG. 1 will be explained below with reference to the flowchart shown in FIG. 4.

First, in step S1, the internal bus 1 of the contents of 5PCa12a is
0 and set this content to 5PCb12b.

Then, in the following step S2, the contents of PO2 are first outputted to the internal bus 10 in order to read the command.
Set the contents of 2 to MAR8. The value set in this MAR8 becomes the read address of the memory 14.

Further, in step S4, the contents of PO2, which are similarly output to the internal bus IO, are set to 5PCa12a. Step S3 and step S4 can be executed simultaneously. Thereafter, in step S5, E of PO2 is incremented by one, and in step S7, the ffIIJ11 circuit 4 instructs the memory control circuit 13 to read the program.

If the content of PO2 is “100”, memory 1
The process of reading out the contents of address "100" in 4 is executed. When the contents of the address "100" are read and set in the MDR 9, this instruction is set in the instruction register 6 in step S6, and the set instruction is decoded by the instruction decoder 7. In step S8, as a result of the decoding, it is determined whether or not it is necessary to read the instruction at the next memory address in order to execute the instruction (one instruction has all been read). In this case, if the address "100" is not a one-word instruction but a two-word instruction or a multi-word instruction, the process returns to step S1;
Executes the reading process of the instruction code at address ``i o i''.

When all the instruction codes necessary for executing the instruction have been read out in step S8, predetermined instruction processing is executed in the subsequent step S9.

$3 To explain the above process using the case of executing the program shown in the figure as a specific example, the execution of the program is now progressing, and the rJMP file stored from address "#100"
When executing the JIJ instruction, “100” is set in PO2.
" is stored there. The contents of 5PCa 12a are transferred to 5PCb 12b, and in order to read the instruction at address "100'' of memory 14, the contents of pcs (100) are output to internal bus 10 and set in MDA8. At the same time, this item is also set to 5PCa12a.

As a result, 'too' is set in 5PCa12a. Then, the value of PO2 is incremented by one, and the read instruction is executed. Since this is a jump instruction, the branch destination J1, that is, "300" PO2
Store in. Then, the process for address "300" is executed.

That is, the value of 5PCa12a for 5PCb12b is 100.
", 300" is set in 5PCa12a, and the word command processing is executed.

Therefore, even if you set a breakpoint at address "300" when depacking a program,
The breakpoint address is set to 5PCa12a in 5PCa,b (12a, 12b) at the break destination, and the address "100" before executing breakpoint processing is set in 5pcb12b.

For this reason, you can easily know where the breakpoint came from in Depack.

Also, in the above explanation, when a break is made from a breakpoint, the contents of 5PCa12a are changed at the break destination. However, if the contents of 5PCa12a are not changed here, only one SPC is required, and the steps described above The processing in S1 is also unnecessary.

E.Other Examples] Also, in the above explanation, an example was explained in which the contents of PO2 are always stored in the 5PC12, but this processing is not always required, and if the program is completed, it may not be necessary. The majority are. Therefore, it is desirable to be able to arbitrarily set whether or not to execute this process using a program instruction.

FIG. 4 shows an arithmetic processing unit that can arbitrarily set whether or not to execute this process based on the program command. Components in FIG. 0 that are the same as those in FIG.

21 in the figure is the SPC set mode register,
It is set by a set command and reset by an SPC reset command. This SPC set mode register 2
The state of S1 is input to the control circuit 4, and the control circuit 4
If the PC set mode register 21 is set, the process shown in I82@ above is executed, and if the spc set mode register 21 is not set, the second
Of the processes in the figure, steps Sl and S4 are not executed.

Further, at this time, input to 5PCa, , b (tza, 12b) is blocked by AND gates 22a and 22b.

E Effects of the Invention J As explained above, according to the present invention, when the program counter for sequentially reading programs is updated,
By automatically saving the contents of the program counter to a storage means and then updating the program counter,
The current program counter value and the previous program counter value can be checked, the execution state of the program can be easily grasped, and program depacking, tracing, etc. can be simplified.

[Brief explanation of the drawing]

@1rRJ is a functional block diagram of an arithmetic processing device according to an embodiment of the present invention, FIG. 2 is an instruction execution flowchart of the embodiment, and FIG. 3 is a diagram showing an example of an execution program. FIG. 4 is a functional block diagram of an arithmetic processing device according to another embodiment of the present invention. In the figure, 2... arithmetic logic unit, 4... control circuit, 5
...Program counter, 6...Instruction register, 7
... Instruction decoder, 8... Memory address register, 9... Memory data register, 12a, b... Program counter save register, 13... Memory control circuit, 14... Memory, 20.・General-purpose register,
21...SPC set mode register, 22...A
It is an ND gate. Figure 2

Claims (2)

[Claims] (1) Holding means for holding the value of the program counter;
counter value saving means for reading the value of the program counter before updating the program counter and storing it in the holding means; saving the contents of the program counter in the storing means when the program counter is updated; , by updating the program counter,
An arithmetic processing device characterized in that it is possible to check a current program counter value and a previous program counter value. (2) The arithmetic processing device according to claim 1, further comprising selection means for selecting whether or not to energize the storage means.