JPH0756637B2 - Processor - Google Patents

Description

The present invention relates to a Neumann type arithmetic processing device having a memory stack function.

[Summary of Disclosure] The present specification and the drawings refer to a Neumann type arithmetic processing device.
By storing the contents of the register being executed in the stack area designated by the stack pointer and setting the stack pointer value to the state before the storage, the contents immediately before the register being executed at the program and at any arbitrary position being executed. You can know
Moreover, it is intended to disclose a technique in which a program execution error does not occur by changing the value of the stack pointer.

[Prior Art] In a conventional arithmetic processing device, arithmetic processing of information is performed in accordance with a program instruction stored in a memory.

Generally, the contents of this arithmetic processing can be arbitrarily changed by program instructions, and it has a modification function so that it can be used for various arithmetic processing. Automatic calculation of arithmetic data with an accumulator (arithmetic logic arithmetic unit) It is performed through a general-purpose register that can be exchanged. In addition to the general-purpose registers described above, the arithmetic processing unit is provided with a program counter, a stack pointer (stack register), a condition code register, a status register, and other temporary registers.

Various arithmetic processes are executed using these register groups, but before the completion of the program instruction or when there is a program error, it is necessary to confirm the execution state of the program instruction by debug processing.

Now, a case will be described in which the debug processing is performed to debug the register operation and the execution time of the arithmetic instruction described below.

L: LD RG1,100 L + 2: LD RG2,101 L + 4: MUL RG1, RG2 L + 6: NOP Here, L to L + 6 are program storage addresses in the memory, and RG1 and RG2 are general-purpose registers having a capacity of 8 bits.

This program is a multiplication instruction that multiplies the contents of RG1 and RG2 and stores the double-precision operation result in RG1 and RG2.
The contents of address 100 are loaded into and the contents of address 101 are loaded into RG2, and multiplication (MUL) is performed. "128" at 100, "25" at 101
If 6 "is stored," 128 "x" 256 "=" 3276
It becomes 8 "(hexadecimal 8000), and the result of the operation is" 8 "in RG1.
"00" and "00" are set in RG2.

Note that the contents of RG1 and RG2 change before and after the multiplication process (MUL). Therefore, if you want to debug the result of multiplication in the middle of the program and want to know the result of the multiplication process, interrupt the program process at the time of executing "LD RG2,101" at L + 2.

Check the contents of RG1 and RG2 at the time of interruption.

Execute "MUL RG1, RG2" at address "L + 4".

Check the contents of RG1 and RG2.

The above procedure is required.

[Problems to be Solved by the Invention] As described in the debugging process of the prior art, when a register operation instruction is executed, the value before execution is destroyed. Had to stop and check the register value at this time, and the process was complicated.

[Means for Solving Problems] The present invention solves the above problems by the following configurations.

That is, in an arithmetic processing device having a stack function using a stack pointer, a storage unit that stores processing information including an execution procedure, an arithmetic unit that performs arithmetic processing of information according to the execution procedure stored in the storage unit, and When at least one register that holds the operation information of the operation unit, a detection unit that detects an operation instruction of the register, and an operation instruction of the register is detected by the detection unit,
Storage means for storing the contents of the register in an area designated by the stack pointer in the storage means prior to the execution of the operation command, and the storage means stores the contents of the register , The value of the stack pointer is restored before the operation instruction of the register is detected.

[Operation] According to the above configuration, it is possible to provide an arithmetic processing unit capable of confirming the contents of registers with a simple configuration using the stack function, and at that time, read the contents of the registers stored in the stack area. Even if the instruction processing is continued without increasing, the data in the stack area is not increased. Further, since the contents of this register are stored in the area which is not used by the normal stack function, there is no influence when the stack function is used for other purposes.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment according to the present invention, in which 1 is a stack register, 2 is an arithmetic logic unit, and 4 is a control circuit. The control circuit 4 performs various timing controls,
This timing control may be configured by hardware (logic circuit) or microprogramming configuration.
With the micro programming configuration, it is possible to easily deal with various processing purposes. Further, 5 is a program counter for storing a memory location of an instruction, 6 is an instruction register, 7 is an instruction decoder for analyzing an instruction of the instruction register 6, 8 is a memory address register, 9 is a memory data register, and 10 is an internal bus. is there. Further, 13 is a memory control circuit, and 14 is a memory. In the memory 14, a stack area 14a is provided. A general-purpose register group 20 is composed of an A register 21 and a B register 22. Here, the general-purpose (calculation) register group 20 can set an arbitrary value by a program instruction.

The operation of the apparatus of this embodiment shown in the drawing will be described below with reference to the flow chart of FIG. 2 as an example of executing the above-mentioned program instruction sequence.

First, in step S1, the program counter (hereinafter referred to as PC)
The value of 5 is the memory address register (hereinafter referred to as MAR) 8
Then, in the subsequent step S2, the value of PC5 is incremented by one.

Then, in step S3, the control circuit 4 instructs the memory control circuit 13 to read the program.

Assuming that the content of the PC5 is "L + 4", the process of reading the content of the "L + 4" address in the memory 14 is executed. "L +
The contents of the 4 "address are read out and stored in the memory data register (hereinafter
When this instruction is set in the MDR 9), this instruction is set in the instruction register 6 in step S4, and the set instruction is decoded by the instruction decoder 7. As a result of the decoding in Step S5,
In order to execute the instruction, it is determined whether or not the instruction at the next memory address needs to be read (all one instruction has been read). In this case, "MUL R" which is an instruction to multiply the contents of the registers A and B at the addresses "L + 4" and "L + 5" and store the result in the registers A and B
G1, RG2 ”is stored and the instruction code at the address“ L + 5 ”must be read subsequently, so the procedure returns to step S1 again.
Read the instruction code at address "L + 5".

When all the instruction codes necessary to execute the instruction have been read at step S5, it is checked at step S6 whether or not the instruction to be executed is a register operation instruction that involves changing the contents of the general-purpose register group 20, and register operation is performed. In the case of an instruction, the contents of the stack register (hereinafter referred to as SP) 1 is MA in step S7.
Store in R8, and then decrement the contents of SP1 by 1 in step S8. Then, in step S9, it is checked whether or not the number of operation registers is one in the register operation instruction to be executed,
If there is one, proceed to step S10, and if not, proceed to step S20.

In step S10, the value of the register to be operated is set in MDR9 and written in the stack area 14a designated by SP1 of the memory 14. Then, in the subsequent step S12, SP1 is incremented by 1 to return to the state before storing the register value, and step 1
It is checked whether or not the register operation instruction to be executed in S13 is an instruction that requires access to the memory 14, and if memory access is required, in step S14 wait for the memory 14 to be out of the access state. Execute (step S15) and then return to step S1.

On the other hand, when the number of operation registers is plural in step S9, the register value to be stored first is set in MDR9 in step S20.

In this embodiment, the A register 21 and the B register 22 are stored in this order.

Then, if the memory 14 is being accessed in step S21, the end of access is waited for, and in step S22, writing to the memory 14 is started.

Here, the value of SP1 is set in MAR8 first, and SP1
Is written in the stack area 14a designated by the above. Then, in step S23, it is checked whether or not the values of all the operation registers have been stored. If not, the value of SP1 is set to MAR8 in step S24, and the value of SP1 is decremented by 1 in step S25. Then, returning to step S20, the value of the next register is written in the stack area 14a.

If the writing of the required register value has been completed in step S23, the value of SP1 is returned to the value before storing the register value in step S26, and the process proceeds to step S13. Then, the register operation instruction is executed.

If the register operation instruction is not found in step S6, the process proceeds to step S27 to execute a predetermined instruction process.

Explaining the above processing with a concrete example, when the program execution is proceeding now and the "LD RG1,100" stored from the "L" address is executed, the content of SP1 is "200". Let's take it.

The control circuit 4 first sets the memory address value "200" indicated by SP1 in MAR8 before executing this register manipulation instruction, and then decrements the contents of SP1. And "RG1"
That is, the contents of the A register 21 are set in the MDR9, and the contents of this MDR9 are written in the stack area 14a designated by the MAR8. Then, SP1 is incremented. This restores the contents of SP1 to the original "200".

Then, the register instruction "LD RG1,100" is executed.

Similarly, in the case of executing "MUL RG1, RG2" at address "L + 4", if the value of SP1 immediately before is "200", RG1 at address "200", that is, the value of A register 21, address "199" RG2, that is, the value of the B register 22 is stored, the value of SP1 is returned to "200", this instruction is executed, and the answer of [RG1] × [RG2] is set in both registers. Therefore, when the instruction is executed from this "L + 4" address in the debugging process, that is, when this process is interrupted before the instruction execution at the "L + 6" address, RG
The contents of RG1 and RG2 are stored in the address indicated by SP1 in the stack area 14a and the address immediately before that in RG1 and RG2, respectively.

Therefore, when the program stops, for example, from the contents of the general-purpose register and the memory address indicated by the stack register 1, a debug program for displaying the memory contents in the lower address direction by the number of general-purpose registers is created, and breakpoints are set. The contents of the current general-purpose register and the general-purpose register immediately before the execution of the current instruction can be displayed at the same time by setting only one position.

Also, since the stack register 1 does not change due to this operation, the above operation does not cause any change to the conventional usage of the stack memory.

In the above description, an example in which there are two general-purpose registers has been explained.
Even if it is more than that, it is exactly the same.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily check the register value state, which has been conventionally complicated, only by using the stack function, and immediately confirm the register state before and after the processing. It is possible to provide an arithmetic processing unit that can be confirmed and that can significantly reduce the load of program debug processing.

Also, after the contents of the register are stored in the stack area, the stack pointer value is restored before the operation instruction of the register is detected, so the instruction processing can be continued without reading the contents of the registers stored in the stack area. However, since the data in the stack area is not increased, and because the register contents are stored in an area that is not used by the normal stack function, it may affect the use of the stack function for other purposes. There is no.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an arithmetic processing unit according to an embodiment of the present invention, and FIG. 2 is an instruction execution flow chart of the present embodiment. In the figure, 1 ... Stack register, 2 ... Arithmetic logic operation unit, 4 ... Control circuit, 5 ... Program counter, 6 ...
... instruction register, 7 ... instruction decoder, 8 ... memory address register, 9 ... memory data register, 13 ...
Memory control circuit, 14 ... Memory, 14a ... Stack area, 20 ... General purpose register group, 21 ... A register, 22 ...
It is the B register.

Claims (1)

[Claims] 1. An arithmetic processing device having a stack function using a stack pointer, a storage means for storing processing information including an execution procedure, and an arithmetic means for performing arithmetic processing of information according to the execution procedure stored in the storage means. At least one register that holds the operation information of the operation means, a detection means that detects an operation instruction of the register, and if the operation instruction of the register is detected by the detection means, prior to the execution of the operation instruction And storing means for storing the contents of the register in an area designated by the stack pointer in the storage means, wherein the storing means stores the value of the stack pointer in the register after storing the contents of the register. An arithmetic processing unit that returns before detecting an operation command.