JPH03134742A - Debug device - Google Patents

Abstract

PURPOSE:To execute the debug without any anxiety by constituting the device so that a mask function interruption (NMI) is not generated in the course of running of a debugger, and also, the existence of an NMI signal generated in the course of running of the debugger can be confirmed. CONSTITUTION:A debug device 15 used for the debug of an application program of a microcomputer system is constituted so that an NMI interruption is not generated by an NMI switch 18 before a debugger 12a is actuated, and also, an NMI signal generated in the course of debug is counted by a counter 20. Accordingly,it does not occur that necessary information is broken down by an NMI in the course of the debugger 12a, and also, it can be recognized that the NMI signal is generated in the course of the debugger 12a. In such a way, the efficiency and the reliability of the debug can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging device used for debugging an application program of a microcomputer system.

[Conventional technology]

Figure 5 is from 80286 Programmer's Reference Manual P, 97. FIG. 2 is an explanatory diagram showing an interrupt descriptor table published by Intel Japan on June 20, 1985. In the figure, 1 is an interrupt descriptor table (hereinafter referred to as IDT; InterruptDescript).
It's called a tor table. ), 2 are constituent elements of IDTl, and are gates that exist as many as the number of interrupt channels that can be handled by the CPU, and 256 gates are prepared. 3
is an IDT register that exists in the CPU, with IDT limit 4 indicating the channel with the highest number among the interrupts actually used in the user's program system, and IDT base 5 indicating the location of the 0th gate 2 in memory. It consists of

Further, FIG. 6 shows the configuration of the gate 2, where 6 is an area that cannot be used by the user, 7 is a flag area that indicates the type of the corresponding interrupt channel, etc., 8 is an unused area, and 9. IO is an interrupt code segment selector and an interrupt code offset in which a code segment and an offset pointing to the start address of an interrupt handler, which is a corresponding interrupt process, are stored.

Furthermore, FIG. 7 shows a debugging device for debugging an application program (hereinafter referred to as a target program) running under a CPU that has software interrupts caused by non-maskable interrupts (hereinafter referred to as NMl) and processor exceptions. FIG. In the figure, 11 is a CPU that executes the target program and the debug program, 12 is a RAM built in the debug device 15 and stores the debug program 12a, a pointer change program (pointer change means) 12b, etc., and 13 is N
A hardware (H/W) abnormality monitoring device that generates an MI signal, I6 is an NMI signal line.

Next, the operation will be explained. When a target program to be debugged is executed on the debug device 15, if an exception such as CFULL zero day byte or segment limit violation is detected due to a defect in the target program, the corresponding interrupt channel ( Generates a software interrupt (hereinafter referred to as an interrupt vector). For example, interrupt vectors 0 to 13 correspond to various types of exceptions. In the debug device 15, when an interrupt handler is activated by these interrupts, a debug program 12a (hereinafter referred to as a debugger) starts operating.

For example, if the interrupt vector corresponding to a segment limit violation is 13, a code segment and an offset pointing to the start address of the debugger 12a are stored in the interrupt code segment selector 9 and interrupt code offset 10 of the 13th gate 2.

When the CPLll1 detects an exception corresponding to the interrupt vector 13, it obtains the physical address where the 13th gate 2 is stored based on the contents of the IDT base 5. Next, the CPU obtains the start address of the debugger 12a from the contents of the interrupt code segment selector 9 and interrupt code offset IO of the 13th gate 2, and obtains the start address of the debugger 12a.
Run 2a.

The debugger 12a displays the value of the CPU II register at the time the exception occurred, in order to display the exception code defined in response to the exception on a CRT (not shown), and to facilitate debugging. It is created to display the instruction that caused the exception or the storage address of this instruction on the CRT.

In addition, normally, even while executing interrupt processing due to a software interrupt or a maskable interrupt caused by an interrupt signal input from the outside, the CPU II
The structure is such that the reception of NMI caused by the I signal cannot be rejected. Therefore, while the debugger 12a is running, NM
Necessary information may be destroyed by I processing, and the same debugging operation may need to be performed again.

In order to solve this problem, if the H/W abnormality monitoring device 13 can be controlled from the CPUI 1, it is conceivable to stop the debugger 12a while it is running. for example,
When an exception occurs and the debugger 12a is started, the exception code m is saved in the RAM 12 of the debugging device 15.
Suspend debugging. Then, in the debug device 15,
A pointer change program 12b is prepared that transfers the debug gate corresponding to the value m of the exception code to the m-th gate 17 of the IDTl. Next, when the target program is executed again with the contents of the m-th gate 17 rewritten to the debug gate, the defect has not been removed, so
The exception occurs again.

Then, after stopping the operation of the H/W abnormality monitoring device 13, the debugger 12a executes a program that is started from the physical address created based on the contents of the debug gate.
If the program is created in such a way that the program transitions to , the NMI signal will not be generated while the debugger 12a is running, so debugging can be performed with peace of mind.

[Problem to be solved by the invention]

Conventional debugging equipment is configured as described above, so NMI information is not completely saved in the target program.
If you are using a processing routine, debugger 1
There was a problem that necessary information was destroyed during 2a driving. In addition, if you start the debugger 12a in such a way that NMl does not occur, NMl, which would normally occur during debugging,
There is a problem in that the I signal is ignored, and the NMI signal, which is useful for debugging, cannot be considered.

This invention was made in order to solve the above-mentioned problems, and is a debugging method that does not generate NMI while the debugger is running and can recognize the presence of an NMT signal that occurs while the debugger is running. The purpose is to obtain equipment.

[Means to solve the problem]

A debugging device according to the second invention includes a CPU having software interrupts due to NMI and software exceptions;
In a device that performs debugging using a debug program connected to an interrupt handler activated by a software interrupt, an NMI switch capable of prohibiting the NMI signal from reaching the CPU, and a counter that counts the number of times the NMI signal is generated; An interrupt disabling program that outputs a switch control signal for opening an NMI switch and cutting off the NMI signal, resetting a counter, and subsequently starting a debugger; and a pointer changing means for connecting the interrupt disabling program to an interrupt handler in place of the debugger. It is equipped with the following.

[For production]

In the present invention, when a software interrupt occurs due to a processor exception, the NMI switch is set to the open side, that is, the side that does not transmit the NMI signal to the CPU, by the interrupt disabling program before the debugger is activated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 12c is an interrupt prohibition program connected to an interrupt handler, 18 is a H/W abnormality monitoring device 13 and C
The NMr switch 19 is provided between the PUII and the NMr switch.
A switch control line to which a switch control signal instructing opening/closing of the MI switch 18 is transmitted; 20 is an interrupt occurrence counter (hereinafter referred to as a counter) for counting the number of NMI signals; 21 is a reset circuit to which a counter reset signal is transmitted. This is a signal line, and the other parts are the same as those shown in FIG. 5 with the same reference numerals.

Next, the operation will be explained with reference to the flowcharts shown in FIGS. 2 to 4. The flowchart in FIG. 2 shows the processing of the pointer change program 12b. First, in step ST21, the contents of each gate 2 of the IDT 1 in the RAM 12 corresponding to the interrupt vectors 0 to 13 are transferred to the RAM 1.
Save it in the evacuation area inside 2. The saved contents of each gate 2 point to the starting address of the corresponding debugger. Then, in step ST22, each gate 2 is rewritten to a debug gate pointing to the start address of the interrupt disabling program 12c shown in the flowchart of FIG.

In this state, run the target program. If an exception occurs during execution, a corresponding software interrupt is generated. Since a debug gate is written in each gate 2 corresponding to the exception, the program shown in the flowchart of FIG. 3 is started after all. When started, first
In step 5T31, the state of the NMI switch 18 is confirmed. If the NMl switch 18 is open (OFF), the process moves to step ST34. If it is closed (ON), the NMI switch is opened (OFF) on the 1st day by the switch control signal, and the counter 20 is opened (OFF) by the counter reset signal 21.
(Step 5T33). Then, from among the contents of each gate 2 of the IDTl saved in step ST21, the one corresponding to the exception that has occurred is retrieved, and the program is started from the address indicated by this contents (step 5T34). In other words, control is transferred to the debugger.

At the end, if necessary, the count value of the counter 20 can be read out to know the number of NMI signals generated while the debugger is running. Note that without performing the process in step 5T31,
The process may always start from step 5T32.

After debugging the target program, the fourth
As in step 5T41 shown in the flowchart of the figure,
The value saved in step ST21 is returned to IDTl.

〔Effect of the invention〕

As described above, according to the present invention, the debug device is configured to prevent the occurrence of NMI interrupts using the NMr switch before the debugger is activated, and to count the NMI signals generated during debugging using the counter. Therefore, necessary information is not destroyed by NMI while the debugger is running, and it is possible to recognize that an NMI signal is generated while the debugger is running, which has the effect of improving debugging efficiency and reliability. .

[Brief explanation of the drawing]

FIG. 1 is a partial configuration diagram showing a debugging device according to an embodiment of the present invention, FIGS. 2 to 4 are flowcharts showing the operation of the debugging device, and FIG. 5 is an explanatory diagram showing the IDT register and the structure of the IDT. , FIG. 6 is a block diagram showing the structure of a gate, and FIG. 7 is a partial block diagram showing a conventional debugging device. 11 is a CPU, 12 is a RAM, 12a is a debugger, 12
b is a pointer change program, 12c is an interrupt disabling program, 13 is a H/W abnormality monitoring device, 15 is a debug device, 18 is an NMT switch, and 20 is a counter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A central processing unit having a non-maskable interrupt caused by an externally input non-maskable interrupt signal and a software interrupt that generates an exception code, and a debug program connected to an interrupt handler activated by the software interrupt. A debugging device that debugs a target program includes: a non-maskable interrupt switch that prohibits the non-maskable interrupt signal from reaching the central processing unit; an interrupt occurrence counter that counts the number of times the non-maskable interrupt signal occurs; After outputting a switch control signal to open a non-maskable interrupt switch and resetting the interrupt occurrence counter,
A debugging device comprising: an interrupt-disabled program that starts the debug program; and pointer change means that connects the interrupt handler to the interrupt-disabled program.