JPH03105529A - Psw type error control circuit - Google Patents

Abstract

PURPOSE:To prevent the abnormality of a control signal by providing a means which detects the end timing of a program interruption and holds a PSW type error if occurred and a means which is shifted to a running state of a control program for a virtual machine mechanism with the contents of the holding means kept at the prescribed value and at occurrence of an interruption. CONSTITUTION:The end timing of an interruption occurred in the running state of a virtual machine or the end timing of a program interruption occurred at detection of a PSW type error is detected by a means 3. Then the means 3 holds the PSW type error occurred. Meanwhile a means 4 is shifted to a virtual machine mechanism control program running state HPV with the contents of the means 3 kept at the prescribed value and at occurrence of a program interruption. As a result, the final flow works continuously up to a W cycle after the loading of the PSW and is shifted to a virtual machine mechanism control program. Thus an instruction fetch or operand access control signal never have the abnormality.

Description

[Detailed Description of the Invention] [Summary Regarding control when a PSW format error occurs in a virtual machine, the real computer is transferred to a virtual machine mechanism for the purpose of preventing the occurrence of an abnormal state when transitioning from the VM state to the HPV state. It is managed by a control program (monitor) and configured to be used as multiple virtual computers, and if a PSW format error occurs while running as a virtual computer, it is processed by transitioning to the running state of the virtual computer mechanism control program. In a virtual computer system controlled as described above, means for detecting the end timing of an interrupt while a virtual machine is running or the end timing of a program interrupt that occurs when no PSW format error is detected, and for holding this when a PSW format error occurs. , the content of the holding means is a predetermined value,
In addition, means for transitioning to a virtual machine mechanism control program running state when a program interrupt occurs is provided.

[Industrial Field of Application] The present invention relates to control when a format error occurs in a program state word (hereinafter also referred to as PSW) in a virtual computer system, and in particular, the present invention relates to control of a virtual computer control program (monitor) when a format error occurs in a program state word (PSW) in a virtual computer system. ) related to control of transition timing.

[Background Art] In an electronic computer, instructions executed by a processor are read from main memory according to a program state word (PSW), and are managed based on the PSW.

The PSW is prepared in advance as a new PSW and old PSW area in a specific area on the main memory according to the type of interrupt, and when an interrupt occurs, the current PSW is replaced with the old PSW depending on the type of interrupt.
The program is saved by writing to the Sw area, and the contents prepared in advance in the new PSW area on the main memory are loaded into the register as the current Psw, and the program read according to the contents of the current Psw is executed by the processor. be done.

If the contents of the PSW are invalid, processing by the processor cannot be guaranteed, so when loading a new PSW, a check is made to see if there is any problem with its format.

At this time, if there is a format error in the PSW, an interrupt (program interrupt) is generated and processing corresponding to the PSW format error is performed.

As described above, the interrupt operation is performed by storing the old PSW at a specific address in the main memory and then loading the contents of the new PSW stored at the specific address in the main memory. However, if the contents of this new PSW are inappropriate,
It also causes a program interrupt due to a PSW format error, which means an endless loop of program interrupts.

Normally, this does not occur because the new PSW is prepared by the OS, but it is quite possible when a newly developed OS is being debugged using a virtual machine mechanism.

For this reason, a new PSW for program interrupts on the virtual machine is required.
If a PSW format error occurs, the hardware is controlled to interrupt the virtual machine control program (monitor).

Specifically, an interrupt to the monitor is an interrupt from the VM state to H
Indicates state transition to PV state. VM state is the state in which a virtual computer runs, and
The V state is a state in which the monitor runs.

In the virtual computer i-machine system, the main memory is divided between multiple virtual computers and monitors, and the base address is assigned to the absolute address that each program is aware of. That is, when an interrupt occurs and a transition occurs to the HPV state when the vibe line is cleared, the monitor wears clogs, and the monitor program is started by reading a new Psw from the allocated main memory area.

Conventionally, when the above PSW format error occurred, HPV
Control is such that the transition to the state is performed immediately when the new PSW is pressed and the state transitions to the process state (PROCESS STATE).

[Problems to be Solved by the Invention] FIG. 3 is a time chart showing an example of conventional control when a PSW format error occurs. As shown in the figure, when the D cycle of the final flow after loading the PSW of the program interrupt processing microprogram starts, the NSI REQ
LCH (NEXT STREAM INST
RUCTION REQUEST LATCI{)
becomes ○N, and using this as a trigger, the state machine executes the end process 7. Te } (END PROCE
SS STATE) to start state (STA
RT STΔTE) to process state (P
ROCESS STATE)l. m transition.

Here, process state latch (PR○CESS
STATE LCH) is OFF and PROCESS
PGM L indicating program interrupt in STATE
Transition to HPV state on condition that CH is ON and PSWFE (format error). PGM L
CH is reset by PROCESS STATE.

In conventional control, PROCESSSTATE is
As a result, the VM/HP
There was a risk that the instruction fetch and operand access control signals affected by V would become abnormal.

In view of these conventional problems, the present invention provides a solution for changing the running state of a virtual machine control program (HP) from the running state of a virtual machine (VM state) when a PSW format error occurs.
It is an object of the present invention to provide a control method that does not cause abnormalities in control signals for instruction fetch and operand access when a transition is made to the V state.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention is configured such that a real computer is managed by a virtual computer mechanism control program (monitor) and used as a plurality of virtual computers.
In a virtual computer system that is controlled so that when a SW format error occurs, the virtual computer mechanism control program transitions to a running state and processes it, detects the end timing of a program interrupt, and detects this when a PSW format error occurs. This is a PSW type error control circuit which is provided with means for holding the above-mentioned holding means at a predetermined value and means for transitioning to a virtual machine mechanism control program running state when a program interrupt occurs.

[Function] In the conventional method, as mentioned above, when a PSW format error occurs while the virtual machine is running, the process state latch is set to FF when the D cycle of the final flow after loading the PSW starts. , because the PGM latch indicating a program interrupt was ON in the process state and a PSW format error occurred, the program immediately transitioned to the virtual machine mechanism control program, so the final flow after loading the PSW was Processing of steps after the D cycle is not guaranteed, which causes abnormalities.

In contrast, in the present invention, the end timing of an interrupt while a virtual machine is running or the end timing of a program interrupt that occurs when no PSW format error is detected is detected, and this is retained when a PSW format error occurs. Control is performed so that when the above-mentioned held content is a predetermined value and a program interrupt occurs, the virtual machine mechanism control program runs state.

Therefore, the final flow after loading the PSW operates up to W cycles and then transitions to the virtual machine mechanism control program, so that no abnormality occurs in the control signals for instruction fetch or operand access.

[Embodiment] FIG. 1 is a diagram showing an embodiment of the present invention, in which 1 represents an AND circuit, 2 an OR circuit, 3 a latch, and 4 an AND circuit.

In the figure, PGM PUPT is a signal that becomes "1" when a program interrupt occurs, START STATE during a start process, and VM STATE when a virtual machine is running. Also, -PSW
When FE does not have psw format error,
This is a signal that becomes "0" when a PSW format error occurs.

FIG. 2 is a time chart showing the operation of the embodiment.

In the same figure, the end process (END PRO) of the line representing the state machine and each displayed state is shown.
CESS). start, start, stay} (STA
RT), process state} (PROCESS) followed by <RSI, RSID is the start state.

VM represents a virtual computer, and HPV represents running of a virtual computer mechanism control program (monitor).

PSW FE outputs “l” when a PSW format error occurs.
”, NSI REQ LCH is a latch that holds the signal requesting fetching of the next instruction, PGM
LCH is a latch that holds a signal indicating that a program interrupt has occurred, and PSW FE ON PX is an output signal of latch 3 in FIG. 1, which is held as "1" when a PSW format error occurs.

When the latch 3 is in the start state or when no PSW format error is detected, the clock enable (
-CLOCK ENABLE) signal is enabled and the contents of the latch are updated.

The latch 3 is manually operated by PGM RURT, START.
When STΔTE and VM STATE are both "1", "1" is held.

That is, in the start state of the program interrupt,
Once the latch 3 attempts to hold "l", it is immediately reset unless there is a PSW format error. If a PSW format error occurs and the signal PSW FE is "0", the latch 3 continues to hold "1" and transitions to the virtual machine Tachibana control program at the timing of the interrupt RSID.

[Effects of the Invention] As explained above, according to the present invention, when a PSW format error occurs, the running state of the virtual machine control program (VM state) is changed from the running state of the virtual machine control program (HP state).
When the transition to the V state is made, no abnormality occurs in the instruction fetch or operand access control signals in connection with this, so there is an advantage that processing loss time can be prevented from occurring.

[Brief Description of the Drawings] Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing the operation of the embodiment, and Fig. 3 is an example of conventional control when a PSW format error occurs. It is a time chart showing. 1.4...AND circuit, 2...OR circuit, 3...Latch

Claims (1)

[Scope of Claims] A real computer is configured to be managed by a virtual computer mechanism control program (monitor) and used as a plurality of virtual computers, and when a PSW format error occurs while running as a virtual computer, the virtual computer mechanism In a virtual computer system that is controlled so as to transition to a running state of a control program and perform processing, means for detecting the end timing of a program interrupt and retaining this when a PSW format error occurs, and the contents of the retaining means are predetermined. , and means for transitioning to a virtual machine mechanism control program running state when a program interrupt occurs.