JPS60142435A - Debugging device of program - Google Patents

Abstract

PURPOSE:To execute flexible program debugging by adding a monitoring data register, a flip-flop (FF) and a selector. CONSTITUTION:The monitoring address register 5 in which an address to be monitored is set by an address monitoring instruction, a monitoring data register 6 to be held at the contents of a main storage device 2 corresponding to said monitoring address and the FF9 for setting any one out of three modes, stop/ interruption/neglect, are formed. Every completion of each instruction execution, the contents of the monitoring address are compared with the monitoring data, and if both contents coincide with each other, the program is branched to the succeeding instruction execution routine. In case of dissidence, the executed operation mode out of said three modes is detected and the program is branched to the corresponding processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program debugging device, and particularly to a debugging device C that is capable of debugging a program by adding only a small amount of hardware.

[Background of the invention]

Traditionally, during debugging during software development, data in main memory is destroyed due to software bugs.
It often runs out of control or stops abnormally. In such cases, the following methods were available to search for the cause of memory corruption.

(() Obtain the memory dump list at the time of abnormal stop,
By detecting a memory corruption area and observing which program was executed using a voice program trace, etc., it is possible to assume the cause of the memory corruption.

However, it has the disadvantage that it takes a long time to determine at what point it will be destroyed.

01) Case with address stop function C specifies the address of the memory destruction area, stops when memory writing to that address is performed, and determines the cause of memory destruction. However, even when writing to the same area, if there is a normal write, and after several normal writes, an abnormal write occurs only rarely, the system stops every time. This has the drawback that it is cumbersome to check the contents of the data while changing the data, and it takes a considerable amount of time to detect an abnormality.

[Object of the Invention] An object of the present invention is to eliminate these conventional drawbacks, to perform flexible program debugging with only the addition of a relatively small amount of hardware, and to eliminate memory corruption causes and program debugging. It is an object of the present invention to provide a program debugging device that can detect abnormalities in a short time.

[Summary of the invention]

In order to achieve the above object, the program debugging device of the present invention includes a monitoring address storage means in which an address to be monitored is set by an address monitoring instruction, and monitoring data that holds the contents of a main memory corresponding to the monitoring address. It has storage means and means for instructing one mode among stop, interrupt, and ignore, and each time the execution of each instruction is completed, the address monitoring routine ``branches'' and stores the address of the monitoring address storage means corresponding to the main address. The contents of the storage device are read out, and the contents are compared with the contents of the 1-memory monitoring data storage means. If they match, the process branches to the next instruction execution routine, and if they do not match, the address is read according to the instructed mode. It is characterized by branching to one of stop processing, address monitoring interrupt processing, and ignore.

[Embodiments of the invention] Hereinafter, a practical example of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a program debugging device showing one embodiment of the present invention.

2 is the main memory, 3 is the address register that holds the main memory access address, raw is the memory buffer register that holds the write data or read data to the main memory, 5 is the address A monitoring address register 6 holds the monitoring address set by the monitoring command, and a monitoring data register 6 holds the contents of the main memory M2 corresponding to the monitoring address.

FIG. 2 is a block diagram of the microprogram sequencer of the present invention, in which 7 is a microinstruction register, 8 is a decoder that selects the control storage address from which to read the next microinstruction, and 9 is an address monitoring branch that generates a microinstruction branch. Interrupt generation circuit 10 that collects a generation circuit, an address monitoring interrupt generation circuit, and other interrupt generation circuits
is the microprogram counter, 11 is +lliW,
Reference numeral 12 denotes a selector that selects one of the contents of the microprogram counter 10, the opcode branch address, and the branch address designated by the microinstruction, according to the designation of the decoder 8.

FIG. 3 is a block diagram of the microphone quadrature control section.

FIG. 3 shows the program debugging device (li[
1) and the microprogram sequencer of FIG. 2. A corresponding microprogram is stored in the control storage device 14 for each machine instruction stored in the main storage device 2.
When a program instruction is read from and set in the memory buffer register, the start address is sent from the operation section of register 4 to control memory address register 13, so that the corresponding microprogram is stored in control memory. The data is read from the device 14 into the anatomical storage data register 7. The contents of the address part of data register 7 are:
Via the microprogram sequencer 20 of FIG. 2, the next address is sent to the control storage address register 13.

The instruction counter 15 in FIG. 3 is omitted in FIG. 1, and the address specified by this instruction counter 15 is the address.
Once set in register 3, the instruction is read from that address in main memory 2 and moved to the memory buffer register.

The operational part of the instruction register is output to the control storage address register 13, while the address part is moved to the address register 3.

The supervisory address register δ of FIG. 1 is conventional, and therefore the present invention combines the supervisory data register 6 of FIG. 1 and the seven lip-flop 9 of FIG.
This can be realized by simply providing a new selector 12.

That is, in the present invention, in addition to the conventional monitoring address register 5 and comparator (calculating unit 1), a monitoring data register 6 is provided, and three types of stop/interrupt/ignoring are provided by the address monitoring command. A 2-bit 7-lip-flop 9 is provided that can set one of the two modes], and the monitor address whose value is set by the same address monitor instruction is held in the monitor address register 5, and at the same time the address at that time is While retaining the contents of the corresponding main memory device 2 in the monitoring data register 6, the contents of the monitoring address and the monitoring data are compared each time after the completion of a subsequent instruction, and if there is a mismatch, The process is divided by detecting which of the previously set δ modes it is in.

Fig. 3 is an operational flowchart of Figs. 1, 2, and 3.

In FIG. 4, ]00 is a general instruction execution, and microinstruction operation 11.0 runs correspondingly. 10
Execution of 1-digit address monitoring instruction, microinstruction operation 1
11 corresponds to kneading. Further, 102 is the execution of a general instruction after the address monitoring instruction is issued, and 12 is executed corresponding to the microinstruction operation.

First, in a general instruction execution 100, a microinstruction is stored in the main memory t2 in the same manner as in a conventional data processing device.
After fetching the instruction and moving it to the memory buffer register raw, the operation section of register 4 is decoded and branched to the first address of the microinstruction group to execute this instruction, and the branch address is transferred to the control memory address register 13. Move to (
1) (2).

The microinstruction read from the branch address of the control storage unit 14 is processed by the decoder 8 if the opcode branch address specification is set in the sequence control field (SC) of the address section. (S C) to select the opcode branch address, selector 12 selects the opcode branch address and selects the control storage address.
This is moved to the register 13, and the microinstruction is read from the branch address of the control storage device 14 and transferred to the control storage address 13 (3).

Then, as each microinstruction is executed, this microinstruction selects 0 in the microprogram counter 10 in the SC field, and stores the address pointed to by counter 10 in the control storage address register 3. At the same time, by decoding the control storage data register 70 micro-operation unit and generating a group of control signals, the arithmetic unit 1 and the main memory 2
etc., and execute micro-instructions sequentially.

Note that depending on the processing of the instruction, there are cases where the microinstruction branches. When the instruction is an address monitoring instruction, microinstruction operation 111 is executed. That is, the microinstruction performs address subtraction described as an operand, and sets the result in the monitoring address register 5 and the address register 5 (]1.)'(2). According to the address of the address register 5, the contents are read from the main memory 2 and stored in the memory buffer register 4 and
1 Set in the monitoring data register 6 via fn (3) (4). In addition, the values of the 2-bit flip-prop 9 are set to (0, 0) and (1, 0), respectively, according to the modes set by the instruction: I↑IL, interrupt, and ignore.

(0,1) (5). This setting can also be done by panel operation.

Furthermore, the start address of the address monitoring routine is set in the BA field of the address portion of the address monitoring branch circuit operation instruction, that is, the microinstruction (6). Then, the next instruction is fetched and the next instruction is executed (7). Once the address monitoring instruction is executed, general instruction execution 1
02, microinstruction operations 112 run until the stop, interrupt, and next address watch instructions are executed (8
). That is, after the microinstruction executes a general instruction α), it branches to the address monitoring routine 2), reads the monitoring address from the monitoring address register 5, and stores Seriton in the address register 3 via the arithmetic unit 1. Read the contents of the main memory 2 at the address (3) (4).

The contents of the read memory buffer register 4 and the contents of the monitoring data register 6 are input to the arithmetic unit 1 and compared, and if they match, the next instruction is fetched and the next instruction is executed. The program then moves on to executing the instructions (5) and (6). If there is a mismatch, the address part of the next read microinstruction is turned off.
By setting the field (judgment instruction), the value of the flip-flop 9 is read out to the decoder 8, and is determined in the decoder 8 (7).

When the value of the flip-flop 9 is (0, 0), it means "stop", so the decoder 8 does not issue a stop instruction among the interrupt factors during program execution, and the stop processing is performed (8). Also, when it is (Ol), it is "ignored", so
The same processing as when there is a match, that is, instruction fetch and opcode branch, is performed (9).

Also, when it is (1, 0), it is an "interrupt", so it is an address monitoring interrupt! Interrupt processing is executed by setting the cause and generating an interrupt from the decoder 8 (
10) (11).

Interrupt processing is a function that interrupts the program being executed and transfers control to another program. Interrupt processing is a function that interrupts the program being executed and transfers control to another program. Interrupt processing due to hardware abnormalities, input/output devices, and other external factors is 9 is asynchronously and preferentially input, and the contents are (0, O), (0, 1), (
For example, (1,1)k-other than 1,0) is changed. When these interrupt factors are set in the flip-flop 9, the selector 12 does not proceed to reading the next instruction, but instead branches to the interrupt control microprogram. Then, when the value of the flip-flop 9 is (1, 0), the processing of the debug function can be made to bypass the interrupt destination software C.

Furthermore, when the value is (0, 0), the program can be stopped and logout can be performed. When the processing by the interrupt processing program is completed, in order to resume the interrupted program, each persimmon status and register contents of the processing device are restored, and execution is resumed from the interrupted point.

In this example, the monitoring address register 5 and the monitoring data register 6 are explained as special hardware; b4
i (prefix area), or if the control storage device 14 is readable and writable, a predetermined area within the control storage device 14 can be allocated.

〔Effect of the invention〕

As explained above, according to the present invention, the normal y+'m
By simply adding a small amount of hardware to m, you can perform flexible program debugging such as stopping when an address comparison and monitoring data match match, or communicating or ignoring software using an interrupt, thereby preventing memory corruption. Causes and abnormal locations can be detected in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a program debugging device showing an embodiment of the present invention, FIG. 2 is a block diagram of a microprogram sequencer showing an embodiment of the present invention, and FIG. 3 is a block diagram of a program debugging device showing an embodiment of the present invention. FIG. 4 is a block diagram of the microprogram control section showing the relationship between the figures, and FIG. 4 is an operation flowchart of FIGS. 1, 2, and 3. l: Arithmetic unit, 2: Main memory, 3 = Address register, 4: Memory buffer register, 5: Monitoring address register, 6: Monitoring data register, 7: Microinstruction register, 8: Decoder, 9 : Interrupt generation circuit (slip flop), 10! Microphone 4 program counter, 11: +1 adder, 12: selector, 13 = control storage address register, 14: control storage, 15:
instruction counter. Patent applicant: Hitachi, Ltd. Attorney: Masatoshi Isomura Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) A monitoring address storage means in which an address to be monitored is set by an address monitoring command, a monitoring data storage means for holding the contents of the main memory corresponding to the monitoring address, and one of stop, interrupt, and ignore. The address monitoring routine reads the contents of the main memory corresponding to the address of the monitoring address storage means for 1 minute each time the execution of each instruction is completed, and stores the contents and the monitoring data. Compare the contents of the means, and if they match, branch to the next instruction execution routine, and if they do not match, branch to one of address stop processing, address monitoring interrupt processing, or ignore according to the specified mode. A program debugging device featuring: