JPS6019028B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION '1} Field of Application of the Invention The present invention relates to control of execution of macro instructions in an information processing apparatus constituted by a main processing unit and a sub-processing unit.

■ Prior Art In recent years, more and more minicomputers are capable of processing floating point arithmetic instructions.

These devices are often composed of a main processing unit and a separate dedicated processing unit (sub-processing unit) whose arithmetic unit has an increased data width so that it can handle floating-point data at high speed. In addition, the main processing unit and the sub-processing unit can operate independently, and the sub-processing unit can be used to perform long processing times such as array calculations and calculations of FJ series. After being activated to execute an instruction, the main processing unit reads and executes the next macro instruction, thereby allowing the two processing units to operate in parallel. Hereinafter, a control flow in which such an information processing apparatus sequentially reads and executes macro instructions stored in a main memory according to a conventional technique will be described.

First, a macro instruction is read from the main processing unit, and when it is decoded and found to be a macro instruction to be processed by the sub-processing unit, the sub-processing unit is activated. At this time, the main processing unit may send the start address of the microprogram to be executed to the subprocessing unit based on the result of decoding the macroinstruction, and the subprocessing unit may start execution from the microinstruction at that address. When adding macro instructions to be processed by the sub-processing unit, the microprogram of the main processing unit must also be changed, so the macro instructions are sent to the sub-processing unit and re-deciphered by the sub-processing unit. An example of such an information processing device is shown in FIG. In FIG. 1, 1 is a main memory (MM), 2 is a main processing unit, and 3 is a sub-processing unit. 4 is a program counter (PC) that indicates the address of the macro instruction to be executed; 5 is an instruction register (IR) that stores the macro instruction read from the MMI; 6
is AN that creates a timing signal to set IR5
This is the D gate.

7 is an AND of a signal instructing to read a macro instruction from the MMI (not shown) and a synchronization signal indicating that data (in this case, a macro instruction) has been read from the MMI.
8 is the IF (lnstrMtiONFetce) signal, and 8 is a clock signal for setting the register.

9 is a circuit (
TEST), and the mother Y flip flop 15 described later
The output signal is one input of the TEST circuit 9.

1 0 is the instruction register (SIR) of the sub-processing unit 3, 11
The circuit (ROM) 12 that generates the starting address of the microprogram that processes it from the macro instruction code stored in instruction register 01 receives the address signal from ROM II as well as the current address plus 11, and the micro instruction. A selector (SEL) is used to select one address signal from among various address signals such as a specified address, and 13 is a control memory address register (CM) that specifies the address of a microinstruction.
14 is a control memory (CM) of the sub-processing device 3.

A flip-flop (BSY) 15 indicates that the sub-processing device 3 is processing a macro instruction, and is set by a START signal 16 for starting the sub-processing device 3 from the main processing device 2.

The BSY flip-flop is reset when the sub-processing device 3 finishes processing the macro instruction. Figure 2 is the first
5 is a timing chart showing the operation of the information processing device shown in the figure. First, in machine cycle T, the main processing unit sends the address of PC4 to MMI, reads out data (macro instruction), and sets it in IR5. Next, in machine cycle L, branching is performed based on the instruction code of the macro instruction just read. Although not shown, this is performed by a control circuit similar to 11 to 14 in the sub-processing device 3. As a result, if the macro instruction is to be processed by the sub-processing device, the machine cycle T2 tests the Y flip-flop 15 of the sub-processing device 3 to determine whether it is possible to start processing a new macro instruction. judge. And if it is possible (BSY 0), START signal 16
is set and the sub-processing device 3 is super activated (machine cycle T4). The sub-processing device 3 receives the BS signal from the STRT signal 16.
When Y flip-flop 15 is set, the macro instruction in IR5 is read out to SIRIO (machine cycle). Next, the output of the circuit 11 that generates the leading number of the microprogram from the instruction code set in SIRIO is selected by SEL12 and set in CMAR13, thereby performing branching based on the macro instruction code (machine cycle T6). After that, the microprogram that processes the macro instruction is executed (machine cycles T7 to L), and the spot Y
Reset the flip-flop 15 and end the process (
Machine cycle T9). During this time, the main processing device 2 is processed by the sub-processing device 3. If the instruction requires a short processing time, such as a floating 4 or several-point arithmetic operation, the Y flip-flop 15 is tested and waited, and the machine cycle T
,. Then, it becomes 0 and the next macro instruction is read (machine cycle T, .). On the other hand, if the macro instruction processed by the sub-processing unit 3 takes a long processing time, such as an array calculation, the next macro instruction is read from machine cycle T3, and the main processing unit 2 also starts processing another macro instruction. do. By the way, looking at the timing chart of FIG. 2, machine cycles T2 to T5 until the sub-processing device starts processing the macro instruction are wasted time for processing the macro instruction. '31 OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a microprocessor in a sub-processing device.

Eliminate wasted time due to canceling the command again,
A macro whose processing unit can be shortened and which is processed by a sub-processing unit. To provide an information device that requires only adding a microprogram to a control memory of a sub-processing unit when adding an instruction. [
4' Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a block diagram of a processing device embodying the present invention, and FIG. 4 is a timing chart showing its operation.

In Fig. 3, 10' is the same instruction register as 10 in Fig. 1, but the input signal is changed so that the data (macro instruction) read from the MMI can be directly set, and the timing signal for setting is also set to IR5. Same as the signal 8, clock signal 9 and BSY flip-flop 15'
(The timing signal is not shown in Figure 1, but the signal obtained by ANDing the signal obtained by decoding the microinstruction that sets SIRI0 and the clock signal is changed.) signal)
. The decoding of whether the macro instruction set in the SIR is an instruction to be processed by the sub-processing unit is substantially performed in the ROMI I', CM 14' without providing a separate decoder. That is, a microinstruction at a predetermined address from ROMII' to CM14' is executed by a macroinstruction. This microinstruction may be one that immediately stops a macroinstruction that should not be processed. When a macroinstruction is to be processed, the process moves to a microinstruction that performs the following predetermined routine work. 20 is S
When the macro instruction set in IRIO' is decoded and it is found that it is a macro instruction to be processed by the sub-processing unit 3, the flip-flop (G
O), and 15' is the same as 15' in Figure 1, but
G when the START signal 16' is received from the main processing unit 2
Set the state of the O flip-flop 20.

Therefore, if the read macro instruction is an instruction to be processed by the sub-processing device 3, the 00 flip-flop 20 is set and becomes 1. If the read macro instruction is an instruction not to be processed by the sub-processing device 3, the GO flip-flop 20 is set. Since it is not set, it becomes 0. GO flip flop 2
0 and BSY flip-flop 15' are reset by a microinstruction when the subprocessing unit 3 finishes processing the macroinstruction. Although 16' is the same as 16 in FIG. 1, it only provides timing for setting the mother Y flip-flop 15' as described above, and has no meaning in starting up the sub-processing device 3.

21 and 22 are AND gates and inverters for creating the set timing of SIRIO'.

14' is the same as 14 in FIG. 1, but the stored microprogram is different as will be described in the operation description below.

The operation of the information processing machine according to the present invention will be explained with reference to FIG.

First, in machine cycle T, a macro instruction is read from the MMI. At this time, the difference from the dependent example is that at the same time the read macro instruction is set in IR5, the subprocessing unit 3 is operating (BSY flip-flop 15' is set to 1).
), set it to SIRI O'.
When BSY flip-flop 15' is 1, sub-processing unit 3 is processing another macro instruction, so
Setting of 0' is not performed. When BSY flip-flop 15' is 0, machine cycle T, SIRIO'
A macro instruction is set in , and activated by the IF signal 8. The activated sub-processing device 3 performs S in machine cycle T2.
According to the address generated in the ROM corresponding to the instruction code of the macro instruction set in IR10', the program branches to a microprogram that processes each macro instruction. S
It is the same as in the conventional example that a microinstruction address is generated from the instruction code of IRIO' by the ROM 11', set in CMAR13, and branched. However, in the present invention, since activation is also performed by macro instructions that are not processed by the sub-processing device 3, a microprogram is prepared in which these macro instructions branch, and the sub-processing device 3 is stopped there. In the case of a macro instruction to be processed by the sub-processing unit 3, the GO flip-flop 20 is set and processing is started (machine cycle T3). On the other hand, after the main processing unit 2 performs a branch due to the macro instruction code, if the macro instruction is an instruction to be processed by the sub-processing unit 3, the BS
The Y flip-flop 15' is tested to determine whether the subprocessing unit was processing another macro instruction (machine cycle T3). When the BSY flip-flop 15' is 1, the newly read macro instruction will not be executed, so in order to inform the software of this fact, the program branches to a microprogram that performs interrupt processing. BSY flip-flop 1 When 5' is 0, START signal 1
Set 6'. GO by START signal 1 6'
The state of flip-flop 20 is set to Y flip-flop 15'. Thereafter, if the macro instruction being processed by the sub-processing unit 3 is an instruction with a short processing time, such as a floating point arithmetic instruction, the CPU 15' is tested and the processing is completed. wait. and,
In machine cycle T7, subprocessing unit 3 finishes processing the macro instruction, resets GO flip-flop 20 and BSY flip-flop 15', and reads out the next macro instruction (machine cycle T9). Also, if the macro instruction is an instruction that takes a long time to process, such as array calculation, M
The next macro instruction is read from the MI, and the main processing unit 2 and sub-processing unit 3 enter parallel operation. When the sub-processing device 3 finishes processing the macro instruction, the sub-processing device 3 issues an interrupt to the main processing device 2 in the same manner as the conventional method used for an input/output device to issue an interrupt to the main processing device. put on. As described above, according to the present invention, the period of machine cycles T2 to T5 described in the conventional example becomes unnecessary, and the processing speed of macro instructions processed by the sub-processing device is improved. In this embodiment, if the sub-processing device 3 is already processing a macro instruction and cannot process the next macro instruction, the GO flip-flop 20 and the BSY flip-flop are used so that the main processing device 2 can determine this. 15' was prepared. but,
If the main processing device 2 and sub-processing device 3 do not operate in parallel, G
O flip-flop 20 plays the role of a BSY flip-flop, and only one flip-flop is required.
Next, a method for adding macro instructions to be processed by the sub-processing device 3 will be explained.

The main processing device 2 performs the same processing as the macro instructions that can be processed by the sub-processing device 3 regarding macro instructions that are scheduled to be added in the future. On the other hand, the sub-processing device 3 is provided with a microprogram that interrupts the main processing device 2 with an illegal instruction code before adding the macro instruction. The method by which the sub-processing device 3 issues an interrupt to the main processing device 2 is the same as the method in which an interrupt is made after finishing the execution of a macro instruction that takes a long processing time. When adding a macro instruction, all you need to do is add the processing program to the control memory of the sub-processing unit. '51 Summary As explained above, <According to the present invention, since the time from when the main processing unit reads the macro instruction to when the sub-processing unit is started is not required, the processing speed of the macro instruction processed by the sub-processing unit is reduced. can be improved.

Additionally, the amount of additional hardware needed to implement the present invention is very small compared to the conventional example.
Furthermore, when adding macro instructions to be processed by the sub-processing device, there is no need to change the main processing device, and it is only necessary to add the macro program of the sub-processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the control of processing of macro instructions read from the main storage device 1 when an information processing device consisting of a main processing device 2 and a sub-processing device 3 is configured according to the prior art. FIG. 2 is the timing chart. FIG. 3 shows one embodiment of the present invention, and is a block diagram of a portion that controls processing of macro instructions. FIG. 4 is the timing chart. 4 illustrations of many boxes

Claims (1)

[Claims] 1 Consists of a main processing unit and a sub-processing unit, and an instruction register provided in each processing unit that reads macro instructions from the main memory and sets them at the same timing, and a register that registers the macro instructions to be processed by the main processing unit. means provided in each of the processing devices for decoding whether the processing instruction is a command or should be processed by a sub-processing device; and if the decoded processing instruction is its own processing instruction, processing the processing instruction; control means provided in each of the processing devices to stop the processing if the decoded processing instruction is not its own processing instruction; and a control means provided in each of the processing devices, and a next macro sent from the sub-processing device to the main processing device. An information processing device comprising: means provided in the main processing device for reading a next macro instruction from the main storage device in response to a test signal indicating that it is OK to proceed to the instruction.