JPS61141038A - Microprogram control processor - Google Patents

Abstract

PURPOSE:To make a microprogram processor into plural chips without increasing the number of terminals by incorporating a sequencer on a master chip and an instruction register and decoder on other slave chips. CONSTITUTION:The microprogram control processor is made into chips, and constituted of an LSI processor 1 built-in the master chip, LSI processors 20 and 30 built-in slave chips and a control memory 2 for storing a micro instruction supplied to said processors. On the chip 10 the sequencer 11 is provided which controls the execution order of micro instructions of chips 10-30 constituted of instruction registers 13-33, decoders 14-34 and control circuits 15, 26 and 37 such as an arithmetic unit. With the indication of the sequencer 11 the micro instruction read out of the memory 2 is transferred to the registers 13-33 of the chips 10-33 and applied to the circuits 15, 26 and 37 after decoding.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control processing device, and in particular, in a microprogram control processing device consisting of a plurality of chips, only a chip serving as a mask has a built-in sequencer. The invention relates to a processing device that controls the execution of microinstructions of a slave chip.

[Conventional technology]

When converting an electronic circuit into an LSI, it may not be possible to integrate it into one chip due to limitations on the number of gates or terminals, and it may be necessary to use multiple chips.

FIG. 2 is a block diagram of a processing device implemented as an LSI.

In FIG. 2, l is a sequencer that controls the execution order of microinstructions, 2 is a control memory that stores a group of microinstructions, 3 is a microinstruction register that stores microinstructions,
4 is a microinstruction decoder for decoding microinstructions; 5, 6.7 are circuits for executing processing; and 8 is a control line for transferring decoded control signals to execution circuits 5, 6.7.

When considering converting this processing device into an LSI, it is impossible to configure the entire device on one chip due to limitations on the number of gates and terminals, and it is necessary to use multiple chips. When using multiple chips, the first method is to install a sequencer 1, an instruction register 3, a decoder 4', and a sequencer 1, an instruction register 3, and a decoder 4' on each chip, as shown in FIG. 3(a). '85-7
There is a way to provide one of these. However, if all the necessary functions are built into each chip, there is a problem in that the amount of hardware increases. Next, as a second method, the third
As shown in Figure (b), the chip 10 serves as a mask.

sequencer l, instruction register 3. Decoder 4° circuit 5
~7 and use the decoded control signals from the master chip to control the other slave chips 40.5
There is a method to control 0. but.

In this method, since the control signal is decoded and then transferred to the slave chip, there is a problem that the number of terminals for both the mask and the slave increases.

[Purpose of the invention]

The purpose of the present invention is to solve such conventional problems and to
It is an object of the present invention to provide a microprogram control processing device that can be configured into multiple chips without increasing the amount of hardware, the number of terminals, and the number of gates of SI.

, [Structure of the Invention] In order to achieve the above object, the microprogram control processing device of the present invention includes a sequencer that controls the execution order of microinstructions, a control memory that stores the microinstructions, and a control memory that stores the microinstructions. In an LSI processing device having a register for storing microinstructions, a decoder for analyzing the microinstructions, and a circuit controlled by the decoder, a master chip including at least the sequencer, the microinstruction register, and the microinstruction decoder;
and a plurality of slave chips including a microinstruction register, a microinstruction decoder, and a circuit controlled by the decoder, which stores microinstructions read out from the control memory under the control of the sequencer of the master block. There is.

〔Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a chip-based microprogram control processing device showing one embodiment of the present invention.

- 1O is an L S and I processing device built into the chip that serves as a mask; 20.30 is an LSI processing device built into a chip that becomes a slave; and 2 is a memory that stores microinstructions supplied to the chips 1O220 and 30. , ll is chip 1
0, 20.30 is a sequencer that controls the execution order of microinstructions; 13, 23.33 is a microinstruction register that stores microinstructions read from control memory 2;
4, 24.34 is microinstruction register 13, 23.3
3 is a decoder circuit for decoding the microphone own instructions; 15, 26, and 37 are circuits such as arithmetic units controlled by the decoders 1, 4, 24, and 34; 9 is a circuit for decoding micro instructions read from the memory 2; Signal lines distributed to instruction registers 13, 23, and 33 of chip 10°20.30, 10-1.
10-2, 10-3 are signal lines for notifying the execution result states of the circuits 15, 26, and 37 in the chips 10, 20, and 30, and 11-1 is the output of the instruction register for the sequencer 1.
A method of generating a first-order microinstruction for 1 (for example, 7
This is a control line that indicates the male address +1).

The microinstructions read out from the control memory 2 by instructions to the sequencer 11 are sent to each chip 1 via the signal line 9.
0, 20, 30 microinstruction registers 13. ．． 23.
Transferred to 33. Microinstruction registers 13, 23 .
The microinstructions stored in 33 are sent to decoders 14 and 24.
．． 34 and are decoded by circuits 15 and 26, respectively.
．． Added to 37. Each circuit 15. ．． 26, 37 indicate the state of the execution result on the signal line 10-1. ,IQ-2,1073
The sequencer 11 in the chip IO is notified through the process.

The sequencer 11 includes a control line 11-1, a signal line 10-1,
10-2. Determine the next microinstruction address based on the content of 10-3. .

In the previous embodiments, the control memory 2 is installed outside the LSI chip, but even if this memory 2 is built into the master chip IO, the operation of the present invention will not be hindered in any way.

〔Effect of the invention〕

As explained above, according to the present invention, the master chip has a built-in sequencer, the other slave chips have built-in instruction registers and decoders, and micro-instructions from the control memory are sent to the instruction registers of all chips. Since each chip was configured to store each, the amount of hardware for each LSI chip.

It becomes possible to use multiple chips without increasing the number of terminals.

[Brief explanation of drawings]

FIG. 1 is an LSI diagram of a microprogram control processing device showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a general microprogram control processing device, and FIG. 3 is a conventional LSI diagram.
1 is a configuration diagram of an SI microprogram control processing device; FIG. 1.11: Sequencer, 2: Control memory, 3゜13.2
3, 33: Instruction register, 4, 14, 24° 34: Decoder, 5, 6, 7, 15, 26, 37: Circuit, 10
, 20.30: Chip. Figure 2

Claims (1)

[Claims] (1) A sequencer that controls the execution order of microinstructions, a control memory that stores microinstructions, a register that stores microinstructions read from the memory, a decoder that analyzes the microinstructions, and a decoder that stores the microinstructions. In an LSI processing device having a controlled circuit, there is provided a master chip including at least the sequencer, a microinstruction register, and a microinstruction decoder, and a microinstruction read out from the control memory under the control of the sequencer of the master chip. A microprogram control processing device comprising a plurality of slave chips including a microinstruction register for storing microinstructions, a microinstruction decoder, and a circuit controlled by the decoder.