JPS61241843A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the generation of undesired interruption and to shorten a debug processing time by saving the contents of a designated register to a designated memory area for each step in a debug mode and producing an interruption only said saving action reaches the boundary of the memory area. CONSTITUTION:In a debug mode a control circuit 7 checks a mask register 4 after execution of each instruction and adds the number of used memory areas to an address register 2 by an arithmetic circuit 5 after saving the contents of a designated register to a memory area designated by the register 2 to replace the register 2. Then the contents of the register 2 and a boundary register 3 are compared with each other. If the value of the register 2 is smaller than that of the register 3, the next instruction is executed. If the contents of the register 2 is equal to or larger than those of the register 3, the circuit 7 produces an interruption to give information to the shoftware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having a circuit effective for debugging programs.

[Conventional technology]

Generally, when developing a program, there is a function to execute the program t-1 steps at a time, a function to display the internal registers of the central processing unit at any point during program execution, and a function to set specific registers to values specified by the program developer. It is necessary to have a function that stops program execution when this happens.

Conventionally, hardware that supports these functions has only had the function of generating all interrupts for each step of the program, reading the internal registers of the central processing unit,
The comparison with a specific value and the display were performed by a program that handled all interrupts for each step.

[Problem that the invention seeks to solve]

In such conventional methods, an interrupt occurs for each step, so one interrupt processing time is required for each step, which takes time for debugging, and also requires buttons and debug processing programs to operate internal registers. The disadvantage is that it is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that solves these drawbacks, shortens debug processing time, and simplifies its processing program.

[Means for solving problems]

The configuration of the present invention includes a register file that stores numerical data, a register selection circuit that selects any two registers in this register file, and an operation on the contents of the two registers selected by this register selection circuit. In the information processing device, the register file includes an address register having a starting address of a memory area for saving the contents of the register; It includes a boundary register that specifies the boundary of the memory area and a mask register that specifies the register to be saved, and when debugging a program, one of the instructions is controlled by the control circuit.
The present invention is characterized in that the contents of the register specified by the mask register are saved in the memory at the end of step execution, and an interrupt is generated when the boundary of the memory area is reached.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a register file, 2 is an address register that specifies the memory address to be saved, 3 is a boundary register that specifies the boundary of the memory area to be saved, 4 is a mask register that specifies the register to be saved, and 5 is an arithmetic circuit. ,
6 is a selection circuit that selects a register in the register file, and 7 is a control circuit that controls the operation of the central processing unit.

When debugging software, when the programmer wants to know the contents of registers for each step, the programmer sets all the numbers of the registers whose contents he wants to know in the mask register 4, and writes them in the starting address register 2 of the memory area that can be used for debugging. In addition, set the boundary address of the memory area for register saving, that is, the address value of the number of instruction steps to be executed, multiplied by the number of register saving areas required for each step, plus the start address, in boundary register 3. After that, switch to debug mode. When set to debug mode, the control circuit 7 checks the mask register 4t at the end of each instruction execution, saves the contents of the specified register to the memory area specified by the 1 address register 2, and then uses the arithmetic circuit 5 to check the mask register 4t. This address register 2 is updated in addition to the security deposit address register 2 of the used memory area.

Thereafter, the contents of address register 2 and boundary register 3 are compared, and if the value of address register 2 is smaller, the process moves to the next instruction execution step. If the value of the address register 2 is equal to the content of the boundary register 3 or the content of the address register is greater, the control circuit 7 generates an interrupt;
Notify the software.

〔Effect of the invention〕

As explained above, the present invention provides a register in a register file that specifies the area where registers are saved, a register that specifies the boundaries of the area, and a register that specifies the register to save. saves the contents of the specified register to the specified memory area,
Generating an interrupt only when the boundary of the memory area is reached has the effect of suppressing the occurrence of unnecessary interrupts and shortening the time required for debugging processing.

[Brief explanation of drawings]

Figure 1 shows the features of the present invention! 1 is a block diagram of one embodiment of an l/j processing device. FIG. In the figure, 1.Old...Register file, 2..Address register, 3..Boundary register% 4..Mask register, 5..
...Arithmetic circuit, 6...Selection circuit% 7...
...control circuit.

Claims (1)

[Claims] A register file that stores numerical data, a register selection circuit that selects any two registers in the register file, and an arithmetic circuit that operates on the contents of the two registers selected by the register selection circuit.
In an information processing device having a control circuit that controls the operation procedure of each of these circuits, the register file includes an address register having a starting address of a memory area for saving the contents of the register, and a boundary between the memory areas. and a mask register to specify a register to be saved, and under the control of the control circuit during program debugging, the contents of the register specified by the mask register at the end of one step execution of an instruction are provided. An information processing apparatus characterized in that the information processing apparatus saves the information in the memory, and generates an interrupt when the boundary of the memory area is reached.