JPH05334098A - Method and device for interruption control - Google Patents

Abstract

PURPOSE:To solve noncoincidence between external interrupt period and internal interrupt processing period by executing processing by external interrupt with the first priority in an interrupt controller used in a device constituted of every kind of internal program and an external interrupt signal. CONSTITUTION:A control signal 123 from an interrupt control means 23 is generated according to the combination of the instruction signal 102 of an instruction generating means 2 and the interrupt signal 101 of an interrupt generating means 1, and the address saving or the address clearing operation of an address saving means 26 can be controlled in detail by the control signal 123, and a second address selection means 12 can be directly controlled by the interrupt signal 101 of the interrupt generating means 1, thereby, it is possible to execute interrupt on all the instructions and to solve the noncoincidence between the external interrupt period and the internal interrupt processing period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling instruction execution of an apparatus (microcomputer, DSP, etc.) which is constituted by an internal instruction program and an external interrupt signal and operates according to the instruction program, and an apparatus for the control. It is about improvement.

[0002]

2. Description of the Related Art In recent years, with the development of digital signal technology, the number of processes digitally controlled by microcomputers and DSPs has increased. However, since the timing of arithmetic processing and the timing of the external interface are not always constant, external interrupt control is required when inputting a signal from the outside.

A conventional interrupt control device will be described below. FIG. 4 is a block diagram of a conventional interrupt control device. In FIG. 4, 1 is an interrupt generating means for generating an external interrupt signal, 2 is an instruction generating means for generating an instruction signal according to an input address, 3 is an interrupt according to each output signal of the interrupt generating means 1, instruction generating means 2. Interrupt control means 4 for controlling, for example, start means for generating a start signal such as power-on or reset operation,
Reference numeral 5 is an address instruction means for giving an address instruction to the instruction generating means 2, 6 is an address saving means for saving the current address 105 according to the control signal of the interrupt control means 3, and 7 and 8 are output addresses and address instructions of the address saving means 6. Adding means for increasing the output address of the means 5, 9 is an immediate address generating means for generating an immediate address 109 in accordance with the instruction signal 102, 10 is the immediate address 109, and the instruction signal 102 from the three addresses 107 and 108. First address selecting means for selecting one address according to the above, 11 for interrupt address generating means for generating an address when an interrupt occurs, 12 for address 110 and interrupt address selected by the first address selecting means 10. Second selection of 111 according to the interrupt control signal 103 Address selection means.

The operation of the interrupt control device configured as described above will be described below with reference to the flow charts of FIGS. 5 and 6.

First, the address designating means 5 designates a predetermined address by the start signal 104 from the starting means 4, and the internal operation is started. The instruction generating means 2 follows the address 105 indicated by the address instructing means 5 in accordance with the instruction 1
02 is output, and the processing is executed according to this instruction. The next operation is determined by the type of this instruction.

First, consider the case where there is no interrupt. Since there is no interrupt, the interrupt control signal 103 causes the second
Of the interrupt selection means 12 is always the first address selection signal 11
Select 0.

(A) In the case of an instruction that does not manipulate the address: The first address selecting means 10 selects the address 108 by the instruction signal 102. Therefore, as the address 112 input to the address designating means 5 as the next address, 108, which is the current address 105 increased by (+1), is selected.

(B) In the case of a subroutine call instruction or a loop count setting instruction (this instruction is hereinafter referred to as a PUSH instruction) In accordance with the interrupt control signal 103, the current address 105 is temporarily saved in the address saving means 6 and the instruction signal 102 The address selection unit 10 of 1 indicates the address 109 indicated by the immediate address generation unit 9 as the next address.
(When the subroutine is called) or address 108 (when the loop count is set) is selected.

(C) In the case of a subroutine return instruction or a loop return instruction (this instruction is hereinafter referred to as a POP instruction) The instruction signal 102 causes the first address selecting means 10 to select the address 107 as the next address. At the same time, the address saved in the address saving means 6 is cleared.

Now, consider a case where an interrupt is input from the interrupt generating means 1 to the above operation. Since a process different from the internal program being executed is temporarily executed by the interrupt, it is necessary to save the current address 105 in the address saving means 6 when the interrupt occurs, as in the case of the PUSH instruction.

However, when an interrupt occurs, the PUSH instruction, PO
If it occurs at the same time as the P instruction, the addresses in the address saving means 6 are accessed at the same time, so that the address of the address saving means 6 is destroyed and the original address cannot be restored.
In the conventional interrupt control device, the PUSH instruction and the POP instruction are saved as interrupt non-permission instructions without executing an external interrupt, the interrupt non-permission instruction is executed as if there was no interrupt, and the next interrupt permission instruction is issued. It takes a method to interrupt when it is executed.

(A) In the case of an instruction that does not operate the address: Since the instruction signal 102 has no information of the instruction not permitting interruption, the interruption is executed, the second address selecting means 12 selects the interruption address 111, and the current address 105 is the address. It is saved in the saving means 6. When the interrupt processing is completed, the first address selecting means 10 receives the address 10 like the POP instruction.
7 is selected, and the address in the address saving means 6 is cleared.

(B) In the case of the PUSH instruction Since the instruction signal 102 has the information of the interrupt non-permission instruction, the address control means 3 stores the address signal 108 in the same manner as when the interrupt control signal 103 does not generate an interrupt. It saves to 6, and holds the interrupt hold information and waits for the next instruction.

(C) In case of POP instruction Since the instruction signal 102 has the information of the interrupt non-permission instruction, the address of the address saving means 6 is set in the same manner as when the interrupt control means 3 does not interrupt the interrupt control signal 103. Along with clearing, it holds interrupt hold information and waits for the next instruction.

According to the above operation, the internal operation including the interrupt is successfully executed.

[0016]

However, in the above-mentioned conventional configuration, when an external interrupt signal is input while an interrupt non-permission instruction is being executed, this interrupt signal is kept until the next interrupt permission instruction is executed. Since it is held, there is a problem that the external interrupt timing does not match the internal interrupt processing timing. In particular, if the interrupt non-permission instruction continues, the timing will be greatly different, so it is necessary to put the interrupt permission instruction at a constant interval. I had.

The present invention solves the above-mentioned problems of the prior art by providing the external interrupt signal with the first priority and making all the commands interrupt-enabled, and the external interrupt timing and the internal interrupt processing timing. It is an object of the present invention to provide an interrupt control device capable of controlling interrupts in which the two match.

[0018]

In order to achieve this object, the interrupt control device of the present invention is such that the output of the interrupt generating means is directly input to the address selecting means immediately before the address designating means, and the interrupt generating means. The interrupt control means and the address saving means for controlling the address saving method for each instruction type by the output of the instruction generating means and the instruction saving means realize all the interrupts as the interrupt enable instruction and the external interrupt signal as the first priority. It has a configuration that can.

[0019]

According to the present invention, since all the instructions are interrupt enable instructions, the present invention can freely create a program without any restriction such as incorporating an interrupt enable instruction in every certain section when forming an internal program. It is possible to realize an excellent interrupt control device in which the interrupt timing and the timing at which interrupt processing is performed internally match.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an interrupt control device according to the first embodiment of the present invention. In FIG. 1, 1 is an interrupt generating means for generating an external interrupt signal, 2
Is an instruction generating means for generating an instruction signal according to an input address, 23 is an interrupt controlling means for controlling an interrupt according to each output signal of the interrupt generating means 1 and the instruction generating means 2, and 4 is, for example, power-on or reset operation. A start means for generating a start signal, 5 is an address indicating means for instructing an address to the instruction generating means 2, 8 is an adding means for increasing the output address of the address indicating means 5, and 9 is an immediate address 109 according to the instruction signal 102. An immediate address generating means, 26 is an addition address 108 and an immediate address 10 according to the control signal of the interrupt control means 23.
9, address saving means for selecting and saving one address from three addresses of its own saved address 126, 10 is an immediate address 109, and 3 of added addresses 107 and 108
First address selecting means for selecting one address from the address according to the command signal 102, 11 is an interrupt address generating means for generating an address when an interrupt occurs, and 12 is selected by the first address selecting means 10. Second address selecting means for selecting the address 110 and the interrupt address 111 according to the interrupt control signal 103.

The interrupt generating means 1, the instruction generating means 2, the starting means 4, the address designating means 5, the adding means 8, the immediate address generating means 9, the first address selecting means 10, the interrupt address generating means 11, the second The address selecting means 12 is the same as the conventional interrupt control device.

The operation of the interrupt control device of this embodiment having the above configuration will be described below with reference to the flow charts of FIGS. 2 and 3.

Since the operation when there is no interrupt is the same as the conventional one, its explanation is omitted here. When an interrupt is generated by the interrupt generating means, first, the second address selecting means unconditionally selects the address 111 of the interrupt address generating means and the interrupt processing is started. Next, the address to be saved in the address saving means 26 is determined according to the instruction 102 at that time.

(A) In the case of PUSH instruction If it is a subroutine call instruction, the immediate value address 109 is saved because the processing returns to the subroutine after the interrupt processing is completed. Further, in the case of the loop number setting instruction, the next instruction is executed after the interruption is completed, so that the address increased by (+1) to the current address 105 is saved. When the interrupt processing is completed, the first address selecting means 10 selects the address 107, but the address in the address saving means 26 is not cleared because the return address by the PUSH instruction is still needed.

(B) POP instruction If a subroutine return instruction or a loop return instruction (the number of loops is other than 0) is returned to the address 126 returned by the address saving means after the interruption, the address 126 is saved again. When the interrupt processing is completed, the first address selecting means 10 selects the address 107, and the POP
The address in the return address saving means 26 is cleared to the return address by the instruction.

(C) In case of other instruction Since the next instruction is executed after the interruption, the current address 10
The address 108 increased by (+1) to 5 is saved. When the interrupt processing is completed, the first address selecting means 10 selects the address 107 and the address in the address saving means 26 is cleared.

As described above, according to this embodiment, according to the instruction 102 of the instruction generating means 2 and the interrupt 101 of the interrupt generating means 1, the interrupt control means 23 causes the address saving means 26 to operate.
By controlling in detail, all instructions can be made to be interrupt enable instructions.
The address selection means can be controlled so that an interrupt can be issued at any time regardless of the instruction.

[0029]

As described above, in the interrupt control device according to the present invention, all the commands generated by the command generating means are set as the interrupt enable commands, and the interrupt signal generated by the interrupt generating means is set as the first priority. Thus, it is possible to perform interrupt control in which the external interrupt timing and the internal interrupt processing timing match.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of interrupt control in the first embodiment of the present invention.

3 is a flow chart of a subroutine in the interrupt control flow of FIG.

FIG. 4 is a block diagram of a conventional interrupt control device.

FIG. 5 is a flow chart of conventional interrupt control.

6 is a flowchart of a subroutine in the interrupt control flow of FIG.

[Explanation of symbols]

 1 Interrupt Generation Means 2 Instruction Generation Means 3 Interrupt Control Means 4 Start Means 5 Address Indication Means 6 Address Saving Means 7, 8 Addition Means 8 Addition Means 9 Immediate Address Generation Means 10 First Address Selection Means 11 Interrupt Address Generation Means 12 Second 2 Address selection means 23 Interrupt control means 26 Address saving means 101 External interrupt signal 102 Command signal 103 Interrupt control signal 104 Start signal 105 Current address signal 106 Saved address signal 107 Addition signal of saved address signal 108 Addition signal of current address signal 109 Immediate address signal 110 First selection address signal 111 Interrupt address signal 112 Second selection address signal 123 Interrupt control signal 126 Saved address signal

Claims (2)

[Claims] 1. An external interrupt timing coincides with an internal interrupt processing timing by setting all the instructions generated by the instruction generating means as interrupt enable instructions and setting the interrupt signal generated by the interrupt generating means as the first priority. An interrupt control method characterized by being capable of interrupt control. 2. An interrupt generating means for generating an external interrupt signal, an instruction generating means for generating an instruction signal according to an input address, an interrupt control means for controlling an interrupt by each signal of the two means, and a start of internal operation. Determining means, an address designating means for starting address designation by a start signal from the starting means, an adding means for increasing an output address of the address designating means, and an immediate value address generating means for generating an immediate value address according to the command signal. Means, address saving means controlled by the interrupt control means, the output address of the adding means, the immediate address of the immediate value means and its own output address being three inputs, and the same three inputs as the address saving means A first selecting one output address according to a command signal of the generating means; Address selecting means, and an output address of the first address selecting means and an output address of an interrupt address generating means for generating an interrupt address to be selected when an interrupt occurs. 1st selecting according to an interrupt signal of the interrupt generating means An interrupt control device comprising two address selecting means.