JPH056280A - Interruption control system - Google Patents

Abstract

PURPOSE:To save labor for reloading a mask value according to a microprogram and to accelerate a processing by switching the mask value of interruption according to the execution address of the microprogram. CONSTITUTION:(n) pieces of interruption mask registers are existent from a register (1) 110 to a register (n) 120. One interruption mask 131 is selected by a mask selection part 130. A mask comparison part 140 compares the interruption mask 131 with an interruption cause 500, interruption 160 is applied to a microprocessor, and the interruption is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system for an information processing apparatus, and more particularly to an interrupt control system having an interrupt mask corresponding to each of a plurality of interrupts and determining the generation of an interrupt depending on the correspondence.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional interrupt control system.

In FIG. 6, 140 is an interrupt mask comparison unit for determining the generation of an interrupt, 150 is a common mask register, 151 is a common interrupt mask output from the common mask register 150, and 160 is an interrupt mask comparison unit 140. An interrupt, 325 is common interrupt mask register write data for setting the common mask register 150, 326 is a common interrupt mask register write instruction, and 500 is an interrupt factor.

In the conventional interrupt control system, a common mask register 150 commonly used is provided, and a common interrupt mask register write data 325 and a common interrupt mask register write instruction 326, which are interrupt mask information, are provided to the common mask register 150. The common interrupt mask 151 is set and the common interrupt mask 151 is output from the common mask register 150. This is a method in which the common interrupt mask 151 and the interrupt factor 500 are compared by the interrupt mask comparison unit 140 and the generation of the interrupt 160 is determined.

[0005]

In the above-mentioned conventional method, an instruction to rewrite the mask value must be executed by the microprogram in order to change the mask of the interrupt, and the instruction is required every time the mask value is set. Therefore, there is a problem that the number of steps of the microprogram increases, which eventually leads to a decrease in processing speed.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to eliminate the trouble of rewriting a mask value in a microprogram, reduce the number of steps of the microprogram, and speed up processing. It is to provide a method.

[0007]

According to a first aspect of the present invention, there is provided an interrupt control system for storing interrupt mask information indicating interrupt mask information indicating whether interrupts of a plurality of interrupt factors are permitted or prohibited. Storage means,
An interrupt mask selecting unit that selects one interrupt mask information from a plurality of interrupt mask information stored in a plurality of interrupt mask information storing units according to a microprogram address being executed, and an interrupt mask selecting unit There is provided interrupt mask comparison means for comparing the interrupt mask information with the interrupt factor and generating an interrupt if the interrupt is permitted.

In the interrupt control system of the second invention, an interrupt mask information storage means for storing interrupt mask information indicating whether to permit or prohibit an interrupt of each interrupt factor for a plurality of interrupt factors, and a plurality of interrupt mask information storage units. An interrupt mask selecting unit that selects one interrupt mask information from a plurality of interrupt mask information stored in the interrupt mask information storing unit according to a microprogram address being executed, and a common interrupt mask information regardless of the microprogram address being executed. Common interrupt mask information storage means for storing the interrupt mask information used for the purpose, interrupt mask information selected by the interrupt mask selection means, common interrupt mask information stored in the common interrupt mask information storage means, and the Compare with the interrupt factor and compare the two And a interrupt mask comparing means for generating an interrupt if it is both permitted interrupt in write mask information.

[0009]

In the first aspect of the invention, the interrupt mask selecting means selects one interrupt mask information from the plurality of interrupt mask information stored in the interrupt mask information storage means according to the microprogram address being executed, and the interrupt mask information is selected. Since the comparing means compares the selected interrupt mask information with the interrupt factor and generates an interrupt if the interrupt is permitted, the interrupt mask can be set by the execution address of the microprogram.

In the second aspect of the invention as well, the interrupt mask comparing means uses the interrupt mask information selected by the microprogram address being executed by the interrupt mask selecting means, and the common interrupt mask commonly used regardless of the microprogram address. The information and the interrupt factor are compared, and an interrupt is generated if interrupts are enabled for both of the two interrupt information, so the interrupt mask can be set by the execution address of the microprogram, and the number of steps of the microprogram can be reduced. .

[0011]

The present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an information processing device including an interrupt control device to which the present invention is applied, which is composed of an interrupt control unit 100, a CS address control unit 200, a microprocessor 300, and a CS 400.

The CS 400 is a memory for storing a micro program executed by the microprocessor 300.
The CS address control unit 200 includes the microprocessor 30.
0 manages the address of the microprogram executed. The CS address 210 output from the CS address control unit 200 is given to the CS 400 and the CS address 21
The microprogram 410 corresponding to 0 is output from the CS 400. When the microprogram 410 is given to the microprocessor 300, the microprocessor 30
0 decodes the microprogram 410 and performs processing according to the instruction. When the executed micro program is a jump instruction or the like, the CS address control signal 310 is given to the CS address control unit 200 to control the CS address. Further, in the case of an instruction such as setting an interrupt mask value, the interrupt control unit control signal 320 is given to the interrupt control unit 100, and the state of the interrupt control unit 100 is set. The interrupt controller 100 compares the interrupt factor 500 with the interrupt mask value and the CS address 210 that have been set, and gives an interrupt 160 to the microprocessor 300 to generate an interrupt.

FIG. 1 is a block diagram of an interrupt control system according to an embodiment of the first invention, and corresponds to the interrupt control unit 100 in FIG.

From FIG. 1, the interrupt mask register (1)
110 (interrupt mask information storage unit), interrupt mask register (N) 120 (interrupt mask information storage unit), interrupt mask selection unit 130 (interrupt mask selection unit), and interrupt mask comparison unit 140 (interrupt mask comparison unit). ing.

There are N interrupt mask registers from interrupt mask register (1) 110 to interrupt mask register (N) 120. The interrupt mask register (1) 110 is constituted by the interrupt mask register (1) write data 321 (interrupt mask information storage means) and the interrupt mask register (1) write instruction 322 (interrupt mask information storage means) by the microprocessor 300 shown in FIG. Set the value instructed by. The interrupt mask register (N) 120 uses the interrupt mask register (N) write data 323 (interrupt mask information storage means) and the interrupt mask register (N) write instruction 324 (interrupt mask information storage means) to cause the microprocessor 300 shown in FIG. Set the value instructed by. Other interrupt mask registers are similarly set. The interrupt mask (1) 111 (interrupt mask selecting unit) to the interrupt mask (N) 121 (interrupt mask selecting unit) set in the above-described interrupt mask register group are input to the interrupt mask selecting unit 130. The interrupt mask selection unit 130 selects one from the interrupt masks input by the CS address 210 (interrupt mask selection means), and interrupt mask 1
31 (interrupt mask comparison means) is output. The interrupt mask 131 is input to the interrupt mask comparing section 140 together with the interrupt factor 500 (interrupt mask comparing means), the corresponding bits are compared, and if the interrupt is enabled, the interrupt is interrupted by the interrupt 160 (interrupt mask comparing means). Occur.

FIG. 4 is a conceptual diagram of interrupt generation of the first invention. In this case, it corresponds to the case of N = 4 in FIG.

CS address 210 is 5000 (hexadecimal)
Consider a case where there is an interrupt factor of 0010 (binary) at the time. At this time, the upper 2 bits of the CS address 210 are 01 (binary), which is used for selecting the interrupt mask register 110, and the interrupt mask 131 is 00.
It becomes 11 (binary). The logical product of the interrupt mask value and the interrupt factor is 0010 (binary). Since the comparison result bit is 1, the interrupt is permitted and the interrupt is generated. Similarly, the CS address 210 is 9000
In the case of (hexadecimal), the upper 2 bits of the CS address 210 are 10 (binary), and the interrupt mask 131 value is 0.
It becomes 100 (binary). 0100 (binary) and 0010
Since the logical product of (binary) is 0000 (binary), in this case, the interrupt is not permitted and the interrupt does not occur.

FIG. 2 is a block diagram of an interrupt control system according to an embodiment of the second invention and corresponds to the interrupt control unit 100 shown in FIG.

The interrupt mask register (1) 110, the interrupt mask register (N) 120, the interrupt mask selecting unit 130, the interrupt mask comparing unit 140, and the common interrupt mask register 150 (common interrupt mask information storage means).

There are N interrupt mask registers from interrupt mask register (1) 110 to interrupt mask register (N) 120. The interrupt mask register (1) 110 sets the value instructed by the microprocessor 300 shown in FIG. 3 according to the interrupt mask register (1) write data 321 and the interrupt mask register (1) write instruction 322. The interrupt mask register (N) 120 sets the value instructed by the microprocessor 300 shown in FIG. 3 by the interrupt mask register (N) write data 323 and the interrupt mask register (N) write instruction 324. Other interrupt mask registers are similarly set. The common interrupt mask register 150 is the same as the conventional example, and the common interrupt mask register write data 3
25 (common interrupt mask information storage means) and the common interrupt mask register write instruction 326 (common interrupt mask information storage means) set the value instructed by the microprocessor 300 shown in FIG. The interrupt mask (1) 111 to the interrupt mask (N) 121 set in the above-described interrupt mask register group are input to the interrupt mask selection unit 130. The interrupt mask selection unit 130 selects one from the interrupt masks input by the CS address 210 and
1 is output. The common interrupt mask 1 output from the interrupt mask 131 and the common interrupt mask register 150
51 (interrupt mask comparison means), interrupt factor 500
Are both input to the interrupt mask comparison unit 140, the corresponding bits are compared, and if the interrupt is enabled, an interrupt is generated by the interrupt 160.

FIG. 5 is a conceptual diagram of interrupt generation of the second invention. This case corresponds to the case of N = 4 in FIG.

The CS address 210 is 5000 (hexadecimal)
Consider a case where there is an interrupt factor of 0010 (binary) at the time. At this time, the upper 2 bits of the CS address 210 are 01 (binary), which is used for selecting the interrupt mask register, and the interrupt mask 131 is 0011.
(Binary). The value 151 of the common interrupt mask register is 0110 (binary). The logical product of these two interrupt mask values and the interrupt factor is 001.
Since it is 0 (binary) and the comparison result bit is 1, the interrupt is permitted and the interrupt occurs. Similarly, when the CS address 210 is 9000 (hexadecimal), the upper 2 bits of the CS address are 10 (binary), and the interrupt mask value 131 is 0100 (binary). The value 151 of the common interrupt mask register is 0110 (binary). The logical product of these two interrupt mask values and the interrupt factor is 0000 (binary). In this case, therefore, no interrupt is permitted and no interrupt occurs.

[0024]

As described above, according to the present invention, the interrupt mask value can be switched by the execution address of the microprogram, and the interrupt mask can be set by the storage address of each module of the microprogram stored in the memory. There is an effect that the trouble of frequently rewriting the mask value by the microprogram can be saved, and the number of steps of the microprogram can be reduced and the processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt control system according to an embodiment of the first invention.

FIG. 2 is a block diagram of an interrupt control system according to an embodiment of the second invention.

FIG. 3 is a block diagram of an information processing device including an interrupt control device to which the present invention is applied.

FIG. 4 is a conceptual diagram of interrupt generation of the first invention.

FIG. 5 is a conceptual diagram of interrupt generation of the second invention.

FIG. 6 is a block diagram of a conventional interrupt control system.

[Explanation of symbols]

100 interrupt control unit 110 interrupt mask register (1) 111 interrupt mask (1) 120 interrupt mask register (N) 121 interrupt mask (N) 130 interrupt mask selection unit 131 interrupt mask 140 interrupt mask comparison unit 150 common interrupt mask register 151 common Interrupt mask 160 Interrupt 200 CS address control unit 210 CS address 300 Microprocessor 310 CS address control signal 320 Interrupt control unit control signal 321 Interrupt mask register (1) Write data 322 Interrupt mask register (1) Write instruction 323 Interrupt mask register (N ) Write data 324 Interrupt mask register (N) write instruction 325 Common interrupt mask register write data 326 Common allocation Inclusive mask register write instruction 400 CS 410 microprogram 500 interrupt factor

Claims (2)

[Claims] 1. An interrupt mask information storage unit for storing interrupt mask information indicating whether to permit or prohibit an interrupt of each interrupt factor for a plurality of interrupt factors, and a plurality of interrupt mask information storage units. Interrupt mask selecting means for selecting one interrupt mask information according to an executing microprogram address from a plurality of interrupt mask information thus generated, and comparing the interrupt mask information selected by the interrupt mask selecting means with the interrupt factor An interrupt control method for an information processing apparatus, comprising: an interrupt mask comparing means for generating an interrupt if the interrupt is permitted. 2. An interrupt mask information storage unit for storing interrupt mask information indicating whether to permit or prohibit an interrupt of each interrupt factor for a plurality of interrupt factors, and a plurality of interrupt mask information storage units. Interrupt mask selection means for selecting one interrupt mask information by the microprogram address being executed from among the plurality of interrupt mask information generated, and the interrupt mask commonly used regardless of the microprogram address being executed Common interrupt mask information storage means for storing information, the interrupt mask information selected by the interrupt mask selection means, the common interrupt mask information stored in the common interrupt mask information storage means, and the interrupt factor, Interrupts can be generated with one interrupt mask information. An interrupt control system for an information processing apparatus, comprising: an interrupt mask comparing means for generating an interrupt if permitted.