JPH0230049B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock comparator control method in a data processing device using a scan loop method.

Figure 1 is a diagram for explaining the outline of the clock/comparator control system, where 1 is the TOD clock (Time Of Day), 2 is the clock comparator register, 3 is the comparison circuit, and 4 is the command to start the microprogram. The flip-flops are shown respectively.

An arbitrary value can be written into the clock comparator register 2 according to an instruction. Comparison circuit 3 compares the value of TOD clock 1 and the value of clock comparator register 2. The comparison result is written to flip-flop 4. Once flip-flop 4 is set, a microprogram for clock comparator interrupt processing is activated.

As the comparison circuit 3, an adder or a matching circuit can be used. When comparator circuit 3 is configured with an adder, the value of TOD clock 1 is
It is possible to configure the adder to output a logic "1" when the value of comparator register 2 is greater than or equal to the value of comparator register 2. However, since the TOD clock 1 and the clock comparator register 2 are each 8 bytes long, they require a large adder and have the drawback of increasing the hardware size.

When the comparator circuit 3 is constructed from a matching circuit, the amount of hardware can be reduced. When a match circuit is used, when the value of TOD clock 1 and the value of clock comparator register 2 are equal, a logic "1" is output from the match circuit.

When a matching circuit is used as a comparison circuit, the following problem occurs. In other words, while CPU operation is stopped and hardware reference is being performed (scan loop is operating and the contents of clock comparator register 2 temporarily change), TOD clock 1 is clocked. - Even if a condition occurs in which the contents of comparator register 2 are exceeded, a problem arises in that a clock comparator interrupt is not generated. Also, the contents of clock comparator register 2 change during scanning,
This causes a problem in that the value of TOD clock 1 and the value of clock comparator register 2 match, and a match output is generated at an inappropriate timing.

The present invention was created in view of this point, and has the following advantages: it is possible to reduce the amount of hardware, it is possible to prevent the situation where clock comparator interrupts that should normally occur disappear due to scan processing, and It is an object of the present invention to provide a clock/comparator control system which is characterized in that it can prevent a situation in which a clock/comparator interrupt occurs due to a clock/comparator interrupt.

[Structure of the invention]

Therefore, the clock comparator control method of the present invention is a clock comparator control method in a data processing device using the scan loop method, and comprises: a TOD clock; a clock comparator register capable of setting a desired value; and the TOD described above. a match circuit that compares the contents of the clock with the contents of the clock comparator register; a scan control circuit that controls scan processing; and a scan control circuit that outputs a predetermined signal when the match circuit outputs a match or the scan control circuit outputs a predetermined signal. The scan control circuit includes a flip-flop that is set when the flip-flop is set, and a clock comparator interrupt processing means that is activated when the flip-flop is set.・The clock comparator interrupt processing means is configured to output a predetermined signal for setting the flop.
When it is started, the magnitude relationship between the value of the TOD clock and the value of the clock comparator register is checked using the arithmetic means in the central processing unit, and if the former is greater than the latter, the program state words are swapped. The invention is characterized in that it is configured to execute a clock comparator interrupt.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the clock/comparator control method of the present invention. In the figure, 1 is a TOD clock, 2 is a clock comparator register, 3 is a match circuit, 4 is a flip-flop that is set by the output of the match circuit 3 or the output of the scan control circuit 5 to start the microprogram, and 5 is a flip-flop that starts the microprogram. scan control circuit, 6
7 indicates other registers, and 7 indicates a scan register.

Any value can be written to clock comparator register 2. The value of TOD clock 1 and the value of clock comparator register 2 are input to matching circuit 3. The matching circuit 3 is
When the value of TOD clock 1 and the value of clock comparator register 2 match, a logic "1" signal is output. The output of the matching circuit 3 is input to a flip-flop 4 via an OR circuit. Flip-flop 4 is set when a logic "1" signal is input. Once flip-flop 4 is set, a microprogram interrupt is started.

The scan control circuit 5 controls the scan process, and outputs a logic "1" signal when the scan process is completed. This logic "1" signal is input to the flip-flop 4 via an OR circuit. Further, the scan control circuit 5 controls the scan register 7. At the time of scan-out, the clock comparator 2 and other registers are connected in series, and the data of these registers is taken out via the scan register 7. Also,
Clock comparator 2 is also used during scan-in.
and other registers are connected in series, and desired values are written into these registers via the scan register 7.

TOD clock 1 value and clock comparator
When the values in register 2 are equal, flip-flop 4 is set. If the CPU is operating when flip-flop 4 is set, clock comparator interrupt processing is immediately initiated. However, if scanning is in progress when the flip-flop 4 is set and the CPU is in a stopped state, clock comparator interrupt processing is started when scanning is completed and the CPU is in an operating state.

FIG. 3 is a flowchart showing a microprogram for processing clock comparator interrupts.

The contents of clock comparator register 2 are read and set in the A register (not shown).

Read the contents of TOD clock 1 and set it in the B register (not shown). Reset flip-flop 4.

The contents of the A register and B register are input to an adder (not shown).

Check whether A-B<0. If Yes, perform the process; if No, perform the process.

Causes clock comparator interrupt
Perform PSW replacement, etc.

Return and perform the next instruction or other interrupts.

〔Effect of the invention〕

As is clear from the above explanation, when an adder is used as a comparison circuit in the clock/comparator control method of a scan loop type data processing device, the hardware becomes large. Since a circuit is used, the amount of hardware can be reduced compared to the case where an adder is used as a comparison circuit. Furthermore, in the clock comparator control method of a scan loop data processing device, when a coincidence circuit is used as a comparison circuit, clock comparator interrupts that should have occurred may disappear, or clock comparator interrupts that should not have occurred may disappear. Although there is a possibility that a comparator interrupt may occur erroneously, according to the present invention, such a situation can be prevented from occurring.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the outline of the clock comparator control method, FIG. 2 is a block diagram showing one embodiment of the clock comparator control method of the present invention, and FIG. 3 is a diagram showing the clock comparator used in the present invention. 3 is a flowchart showing a microprogram that performs interrupt processing. 1...TOD clock, 2...Clock comparator register, 3...Comparison circuit composed of a matching circuit, etc., 4...Flip-flop, 5...
Scan control circuit, 6...other registers.

Claims (1)

[Scope of Claims] 1. A clock comparator control method in a data processing device using a scan loop method, comprising: a TOD clock; a clock comparator register capable of setting a desired value; and the contents of the TOD clock and the above. A match circuit that compares the contents of the clock comparator register, a scan control circuit that controls scan processing, and is set when the match circuit outputs a match or when the scan control circuit outputs a predetermined signal. The scan control circuit includes a flip-flop and a clock comparator interrupt processing means that is activated when the flip-flop is set, and the scan control circuit sets the flip-flop when the scan process is completed. The clock comparator interrupt processing means is configured to output a predetermined signal for
When it is started, the magnitude relationship between the value of the TOD clock and the value of the clock comparator register is checked using the arithmetic means in the central processing unit, and if the former is greater than the latter, the program state words are swapped. A clock/comparator control method, wherein the clock/comparator is configured to execute a clock/comparator interrupt.