JPH01184545A - Microprocessor - Google Patents

Abstract

PURPOSE:To accept interruption in breaking and to execute the interruption processing of an application program in an emulator by providing a circuit to mask a privilege mode signal which becomes input to an interruption prohibition circuit. CONSTITUTION:When an interruption request is generated at the time of setting a register 5 at '0', the interruption processing is started after an instruction being executed at that time is completed, and a signal INT is outputted. After that, a recovery instruction is executed after an interruption processing routine being executed, and a program status word is recovered from a stack, then, a signal RETI is outputted. The output Q of an R-SFF 8 goes to '1' by the above signal, and an alternate memory 2 becomes active, and the execution of a monitoring program is restarted. As mentioned above, when the interruption is applied in a privilege interruption mode, the interruption processing of the application program can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microprocessors, and more particularly to microprocessors with privileged interrupts and privileged mode signals.

[Conventional technology]

FIG. 5 is a partial diagram of an emulation device using a conventional microprocessor. An emulation device is a device that efficiently depacks application programs created by the user.It replaces the user system, executes application programs in real time (hereinafter referred to as emulation), and uses the addresses set by the user. It has functions such as interrupting the emulator 3 when a program is executed (hereinafter this state is called a break), displaying the contents of the registers at that time, and displaying and rewriting the contents of memory and registers.

Since the application program is stored in the alternative memory 3 and is not in the privileged mode during emulation, the SVMODE signal representing the privileged mode is at the "O" level, and the SVM output from the microprocessor 1'
Alternate memory 2, which uses the ODE signal as chip select (O8) input, is inactive because the chip select is a positive logic input, and alternative memory 3 is active because the chip select input is negative logic, and the application program on alternative memory 3 is is executed.

When the program is executed at the address set by the user where the user wants to cause a break, a privileged interrupt request signal a is generated from a break circuit (not shown) in order to enter the break state, and the privileged interrupt input terminal SVI of the microprocessor 1' is is input. When the microprocessor 1' accepts the privileged interrupt -t, it outputs the privileged mode signal SVMO.
DE is set to "1". This allows the microprocessor to
The internal interrupt disabling circuit disables the acceptance of interrupts because the input SVMODE signal becomes "1". Further, the alternative memory 3 becomes inactive, and the alternate memory 2 becomes active, and the monitor program stored in the alternative memory 2 is executed, resulting in a break state.

[Problems to be Solved by the Invention] In the emulation device using the conventional microprocessor described above, all interrupts are disabled during a break state in which no application program is being executed.

This becomes a problem in the following cases.

FIG. 6 shows how the microprocessor 1' controls the DC motor 1.
It is a system that controls 3.

In the partial diagram of the user system, the port output of the microprocessor 1' is connected to the input of a four-pass filter 120, and the output of the low-pass filter 12 is the power supply voltage of the DC motor 13. The port output of the microprocessor 1' is processed by a routine to handle overflow interrupts that occur each time the built-in timer completes a cycle and overflows.
It is set to "1". It is also set to "0" by the timer interrupt processing routine that occurs when the preset value and the timer count value match. The setting value for this timer interrupt If you increase the timer interrupt, the occurrence of the timer interrupt will be delayed, so the period in which the port output is "1" will be lengthened accordingly. This timing is shown in Figure 7. The port output is filtered by the low-pass filter 12.
Since the voltage changes, the rotation speed of the DC motor 13 can be controlled by this voltage.

In this system, the port output is changed by the interrupt processing routine, so when depacking a program on this system using an emulation device, when a break occurs, interrupts are disabled and the port output changes to the value immediately before the break. It will remain unchanged and will not change. If the port output is “1” at the time of break, the output of the low-pass filter 12 will be the maximum voltage, and the DC
The maximum voltage remains applied to the motor 13.

If left in this state for a long time, the fill of the DC motor 13 may burn out due to overvoltage, which is a serious problem.

[Means for solving problems]

The microprocessor of the present invention includes a circuit that masks a privileged mode signal that is input to an interrupt disabling circuit, and a circuit that outputs a signal from the time an interrupt other than a privileged interrupt occurs until the execution of the return instruction for that interrupt is completed. A circuit to
It has a circuit that masks the privileged mode signal using the signal.

〔Example〕

FIG. 1 is a partial diagram of an emulation device using a microprocessor according to a first embodiment of the present invention.

Register 5 is a register that sets whether the microprocessor 1 is set to a mode in which interrupt processing is performed in privileged mode or not. The mode is set to allow processing.

The R-8 flip-flop 8 is an interrupt mode signal generation circuit that outputs an interrupt other than a privileged interrupt until the execution of the return instruction for that interrupt is completed. The output of a two-man OR gate 6 receives the output Q and the RETI signal indicating that the return instruction from the interrupt has been completed, and the reset input R receives the INT signal indicating the start of interrupt processing. Note that when both the reset input R and the setter input S are "1", the output Q is "1". Moreover, the output Q is connected to the input of the two-man power AND gate 9, and the two-man power AND gate 9 is connected to the input of the two-man power AND gate 9.
It is connected to the other input of the D gate 9 and serves as a mask signal for the privileged mode signal SVMODEO which outputs "1" during the privileged mode.

The interrupt disable circuit 4 is a circuit that disables the generation of interrupts by inputting "1" to the input, and the input is a register 5.
The output Q of the two-man power AND gate 7 whose input is the output SVMODE of the two-man power AND gate 9 is connected.

The SVMODE signal of the microprocessor 1 is input to the chip select input C8 of the alternate memory 2 and the alternate memory 3, and the addresses AO to 15 and data DO to 7 of the microprocessor L are respectively It is connected. Also, alternate memory 2
3 is a memory that becomes active during a break and stores a monitor program, and an alternative memory 3 is a memory that becomes active during emulation and stores an application program.

In this embodiment, it is specified that register values are not destroyed in the interrupt processing routine, and that the stack pointer is not used in the monitor program.

First, the operation when "1" is set in the register 5 will be explained.

Since the output Q of the register 5 is “1”, the two-man OR gate 6
The output of is "1", and the output Q of the R-S flip-flop 8 is always "1". Therefore, the output SVMODE of the two-man power AND gate 9 is the same as the input SVMODEO signal. Also, one input of the output of the two-man power NAND gate 7 is connected to the output Q of the register 5, which is 1
', so it is the same as the SVMODE signal. Therefore, if you are not in privileged mode, set SVMODEO="O"
VMODE is also “O” and the input of interrupt disable circuit 4 is “0”.
”, interrupts are enabled, and since the chip select input C8 of the alternative memory 3 is “0”, it becomes active and the application program is executed. Also, in privileged mode, SVMODEO is “1” and SVMODE is also “1”. ”, the input of the interrupt disable circuit 4 is “1” and interrupts are disabled, and the chip select input O8 of the alternate memory 2
Since it is "1", it becomes active and the monitor program is executed.

As described above, when register 5 is set to "1", interrupts are disabled during the break state, that is, during the privileged mode, and the operation is the same as before.

This mode can prevent an interrupt from occurring during a break and causing a runaway during execution of the interrupt processing routine when the application program is being debugged at an early stage and the interrupt processing routine is not fully operational.

Next, the operation when the register is set to "0" will be explained.

Since one of the inputs of the two-manual AND gate 7 is the output Q of the register 5 which is "0", the output is "0" and the interrupt disabling circuit 4 is in the interrupt enabled state regardless of the state of the SVMODE signal.

The R-8 flip-flop p, p8 has the output Q of the register 5 “
1" → "0" and the output of the two-man OR gate 6 becomes "0".
”, the output Q remains “1”. In this state, a signal is input to the privileged interrupt request SvI input from a, the privileged interrupt is accepted, and the SVMODEO signal is “
1”, the output SVMODE of the two-man AND gate 9
also becomes "1", the chip select input C8 of the alternate memory 2 becomes "1", the alternate memory becomes active, and the monitor program is executed.

When an interrupt request is generated here, after the instruction being executed at that point is completed, interrupt processing begins and an INT signal is output. This signal resets the R-S flip-flop 8, the output Q becomes "θ", and the output SVMODE of the two-manual AND gate 9 becomes "0", making the alternative memory 3 active. Save the program count program status word to the stack on alternative memory 3,
Branches to the interrupt processing routine and ends the interrupt processing. Thereafter, after executing the interrupt handling routine, a return instruction from the interrupt is executed, the program status word of the four-gram counter is returned from the stack, and the [TI signal is output]. Due to this signal, the output Q of the R-8 flip-flop 8 becomes "1", the SVMOD E signal becomes "1", the alternate memory 2 becomes active, and the execution of the monitor program is resumed. , the timing of each signal at this time is shown in FIG.

As explained above, if register 5 is set to "0" and an interrupt request is made during break state, that is, privileged mode, an interrupt will be generated and the interrupt processing routine of the application program in alternative memory 3 will be executed. I can do things.

FIG. 3 shows a microprocessor according to a second embodiment of the present invention.

FIG. 2 is a partial diagram of an emulation device using a

The only difference in the first embodiment is that the interrupt mode signal generating circuit outputs the signal from the time when an interrupt other than a privileged interrupt occurs until the execution of the return instruction for that interrupt is completed, and other parts are the same.

The operation of this interrupt mode signal generation circuit will be explained.

When not in privileged mode, SVMODEO signal is “0”
Therefore, the reset input R of the hexadecimal up-down counter 10 becomes "0", and the counter 10 is in the reset state. The outputs of the counter 10 at this time QA, QB, Qc,
All QDs become "0". After this, the mode enters the privileged mode, and when SVMODEO is 1', the enable input EN of the counter 10 is "1", so the count is not enabled and the outputs QA, QB, Qc, and QD are If all remain at "O", the output of the four-person NOR game) 11 remains at 1', and the privileged mode signal is not masked, so the operation is similar to that of the prior art. When the output Q of the register 5 is 0'', the counter 10 is enabled to count, and due to the occurrence of an interrupt, the INT signal becomes ``1'' and becomes an up-count input for the counter 10, so it is counted up, and the output is QA= 1.Q
! 1 = 0°Q, = 0, QT, = 0, the output of the four-man power N0IR gate 11 becomes "0", the privileged mode signal SVMODE becomes "0", and the interrupt on the alternative memory 3 is generated as in the first embodiment. Execute processing routines. Here, when multiple interrupts, which were not allowed in the first embodiment, occur, the INT signal becomes "1" again, the counter 10 counts up further, and the output is QA=0. Q! 1=1
．． Qc=O, and the output of the four-man power NOR gate 11 is “O”.
”, so the program in the alternative memory 3 is executed as it is. When the return instruction of the multiple interrupt is executed and the RETI signal becomes “1”, the counter 10 counts down and the outputs are QA=1.QB= O, Qc=0.
When QD=0 and the return instruction for the first interrupt is executed and the RETI signal becomes "1" again, the counter 1
0 is further counted down and the output is QA.

qB+ Qc-QD all become "0", the output of the 4-man power NOR gate 11 becomes "l", and the SVMODE signal also becomes "1"
Execution of the monitor program on the alternate memory 2 is then resumed. The timing of each signal at this time is shown in FIG.

Even when multiple interrupts are received in this manner, the counter 10 operates normally up to the maximum level of 15 types as long as the counter 10 does not overflow. Normally, even if multiple interrupts occur, there is no problem as long as you have up to 2 circuits and up to 15 circuits.

In the second embodiment, even when multiple interrupts occur in this way, the interrupt processing routine of the application program can be executed normally.

〔Effect of the invention〕

As explained above, the microprocessor of the present invention has a circuit that masks the privileged mode signal that is input to the interrupt disable circuit, an interrupt mode generation circuit, and a circuit that masks the privileged mode signal with the signal. In the emulation device, there is an advantage that interrupts can be accepted during a break and the interrupt processing routine of the application program can be executed.

[Brief explanation of the drawing]

FIG. 1 is a partial diagram of an emulation device using a microprocessor according to a tenth embodiment of the present invention, FIG. 3 is a partial diagram of an emulation device using a microprocessor according to a second embodiment of the present invention, and FIG. FIG. 6 is a partial diagram of an emulation device using a microprocessor, FIG. 6 is a partial diagram of a system for controlling a DC motor using a microprocessor, and FIG. 7 is a timing diagram of each part during motor control. FIG. 2 is a timing diagram when an interrupt occurs during the privileged mode of the first embodiment, and FIG. 4 is a timing diagram when an interrupt occurs during the privileged mode of the second embodiment. 1...Microprocessor of the present invention, 1'...
...Conventional microprocessor, 2...Alternate memory, 3...Alternative memory, 4...
...Interrupt disable circuit, 5...Register,
6...2-person OR gate, 7.9...
2-person AND gate, 8...R-8 flip-flop, 10...Hex up/down counter, 11...4-person NOR gate, 12...
...Low pass filter, 13...DC motor. Agent Patent Attorney Uchihara Oto A) No. 5 Zuyaku 2nd time

Claims (1)

[Claims] It has a privileged interrupt and a return instruction from that interrupt, and a privileged mode signal that is output from the time a privileged interrupt occurs until the execution of the return instruction for that interrupt is completed, and an interrupt that uses that privileged mode signal as input is disabled. In a microprocessor having a circuit, a circuit that masks a privileged mode signal that is input to an interrupt disabling circuit is provided, and a circuit that outputs a signal until a privileged interrupt occurs and the execution of a return instruction for that interrupt is completed; A microprocessor comprising a circuit that masks the privileged mode signal using the signal.