JPS6159537A - Interruption controller - Google Patents

Abstract

PURPOSE:To utilize effectively an interruption input even if it is masked by dividing an m-bit interruption input into a mask object bit and a non-mask object bit, using a mask bit as a part of an input data and transmitting it to a data bus. CONSTITUTION:An m-bit in an input data 8-bit given to an input port 39 is stored in an interruption request register 38 as an interruption input. A selection circuit 35 selects the mask bit and the non-mask bit among the set m-bit in the register 38 based on the mask data stored in a mask register 36 and the mask bit is transmitted to a data bus (e) via an output line (g) as a part of the input data. Further, the non-mask bit is outputted to a priority encoder 34 via an output line (h). The encoder 34 processes the non-mask bit inputted therefrom. Thus, the interruption input in mask state is read to a microcomputer I as a part of the input data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to interrupt controllers, and more particularly to techniques for processing interrupt inputs in a masked state.

(The back of the invention) The conventional interrupt controller has an interrupt input of jh3.
If it is not the 17th mask, it determines whether it is the 17th mask or not, and if it is not to be masked, it issues an interrupt request signal to the microcomputer, sends the interrupt cause data to the data bus, and executes a predetermined interrupt. Place 1! My [1 computer is configured not to sense masked interrupt inputs.

However, in some systems implemented with microcomputers, such as sequence control systems implemented with programmable controllers, it is not possible to accurately grasp changes in events if the masked interrupt corner is disabled. This is often the case.

Furthermore, depending on the nature of the event, it may be appropriate to subject it to interrupt processing only in certain cases, and to subject it to general data processing in other cases.

This invention was made based on such knowledge.

(Object of the Invention) An object of the present invention is to enable a microcomputer to process interrupt inputs by handling data bits to be masked as part of the input data.

(Structure and Effects of the Invention) In order to achieve the above-mentioned object Ia, the present invention provides processing of input data carried on a data bus and predetermined processing in response to an interrupt request signal input to an interrupt port. a mask register that stores mask data sent to the data bus by a microcomputer that performs interrupt processing; and m bits that are extracted from the input data that is placed on the data bus based on the contents of the mask register; An 11-input request register that performs υI-input manually, and divides the 01-bit interrupt input stored in the interrupt request register into mask target bits and non-mask 7=l elephant bits based on the contents of the mask register. , the bits to be masked are sent to the data bus as part of the input data,
For non-masked burnout bits, when a request signal is issued to the microcomputer, the interrupt cause data is used as input data (above)? - A control unit that sends data to the bus.

With this configuration, if a specific m bit of input data is to be unmasked, it will be treated as a target for interrupt processing, and if it is to be masked, it will be treated as a target for general data processing. Because it is large, you can accurately grasp the changes in the @ elephant [not the control vs. Z! It is possible to design a flexible system according to the character of the person.

(Description of Embodiment) FIG. 1 does not show an interrupt controller according to an embodiment of the present invention.

In the figure, the microcomputer 1 receives a control signal (R
By controlling the path buffer 2 with /'W>, the input data transferred to the data bus a via the director 31 is transferred to the internal data bus, and the output data is transferred to the data bus. It performs the operation of sending data to the bus C and the operation of interrupt processing in response to the interrupt request signal d input to the interrupt port INT.

An interrupt controller 3 is connected to this microcomputer 1 h8. .

This interrupt controller 1-roller 3 includes the selector 31, decoder 32, control circuit 33, priority encoder 3/I, selection circuit 35, etc., and two mask registers (#) connected to the data bus C. 1. #2) 36 and 37, an interrupt request register 38, and an input port 39 into which 8-bit data is input.

The decoder 32 decodes the address data bits (AD to A15) output by the microcomputer 1 and provides each output to the control circuit 33.

The control circuit 33 receives each output of the decoder 32 and outputs an R11J control signal to each of the above elements. That is, each of the above elements operates under the control circuit 33.

The 8-bit data input to the input port 39 is input to the selector 3'1 via the data bus C, and
The interrupt request register 38 is input via the data bus r.

The interrupt request register 38 has m bits (m≦8) of the 8 bits of input data given to input iI: -1-39.
) are stored as interrupt inputs, etc. The mask registers 36 and 37 store mask data sent to the data bus C, and there are 12 types of mask data -(, .

In other words, the mask register 37 is the interrupt request register 3
This is for specifying the m bits to be stored in the mask register 37. Such mask data is stored in this mask register 37.

Further, the mask register 36 specifies a mask bit in the 01-bit interrupt input stored in the interrupt request register 38, and such mask data is stored in this mask register 3 (5).

Based on the mask data stored in the mask register 36, the selection circuit 35 selects the back mask bits and non-mask bits stored in the mask request register 38, and the mask bits are A portion of the input data is sent to the data bus e via the output line q.The non-mask bit is output from the output line 11 to the priority encoder 34 (187). ?Subbit 1~ is processed. That is, when the interrupt request signal d is generated, 3-bit interrupt cause data is output to the selector 31 via the data bus k.

At this time, if there are multiple non-masked bits, that is, 15
If there are multiple interrupt inputs, the above operation is performed for all interrupt inputs when the interrupt level is high.

The selector 31 performs an operation of changing the data buses e and 1 to V) and connecting them to the data bus a.

With this configuration, mask registers 36 and 37
By appropriately determining the contents of the mask data in the charcoal oven 11, it is possible to allocate specific 11 bits behind the S-bit input data as the 91-bit input, and mask out of the allocated m-bit interrupt inputs. The interrupt input in the state 1! is read into the microcomputer 1 as part of the input data. :Can be done.

Next, a specific example of application of this J: Eel interrupt controller 3 is shown in FIG.

FIG. 2 shows a programmable controller to which the present invention is applied.

As is well known, the programmable controller is located at the central location! I! The device (CPU) 21 is the main unit, and the data bus and address bus of the CPU 21 include a memory 22 in which system programs are stored, a memory 23 in which user programs (8) are stored, An input circuit 24 to which a plurality of input signals IN are applied, an output circuit 25 to send out a second output signal OUT, and a memory 26 in which input/output data is stored are connected to each other.

The CPU 21 operates according to a system program, stores a plurality of input signals IN given to the input circuit 24 in a predetermined area of the input/output memory 26, and stores the input signals IN in the memory 23.
A user program execution process that reads out each euzo ω instruction of the user program stored in the memory 26, performs arithmetic processing based on the input/output data stored in the memory 26, and sets the processing result in the output area of the memory 26. , and the operation of sending the output data set in the output port of the memory 26 to the output circuit 25 are basically performed.

In the programmable controller that operates in this manner, the input circuit 24 is provided with two output ports (X, Y), and one output port X serves as one input of the pass buffer 27. The other output port Y of the input circuit 24 is input to the other path buffer 27 via the interrupt controller 3.

The path buffer 27 switches both input data and sends it to the CPU 21.
At the same time, the mask data to be multiplied on the data bus is sent to the interrupt controller 3 at L5.

In other words, a plurality of input signals IN input to the input circuit 24
The sign is connected to a specific input terminal.
~ is input to the roller 3. Figure 3 represents the user program stored in the memory 23 in the form of a relay ladder diagram.

For example, this user program controls the water level of tank J, and after the water level of the tank exceeds 80% of the water level, the water injection into the tank will be finely controlled.
151 Let us consider the case where the water level is adjusted in an efficient manner.

In the program △, the AND condition of relays 1, 2, and 3 is satisfied, the counter CN is activated, and the logic state of relay 4 is set to the counter CN.
This indicates that the counting operation 1' of the counter CNT is to be continued or stopped.

In this case, relay 3 is the output signal of the flowmeter and also serves as an interrupt input.

Further, the counter CN is designed so that the water level in the tank can be determined from the count lr(), and is set to emit a count up signal when the count value reaches 80% of the full water level.

Program B (Yo, the count up of the above counter is 18
Indicates that the mask release flag F is set or reset depending on the logic state of the relay CNT10.3 Program C is an interrupt processing program, and this interrupt processing program includes relay 3. Contains a program for when an interrupt input occurs.

As is well known, the operation of the execution process of the knee 1 abprogram (
This J3 reads the user commands sequentially from the start address of the program memory 23 and executes them, and when the end of the 1-11 program is indicated and the ENDω instruction is read, the program returns to the start address again. ,Ko+1 is near V
.

In the process of repeat execution like this, the mask release flag F
During the IVj interval T, which can reach the rehit 1m, the relay 3 becomes the mask target and the J series.When the program Δ is executed, the output of Nagareyama i1 becomes the count input of the counter CNT,
The inflow water m into the tank is run one by one.

This state can be known by monitoring the count 1-1 of the counter CNT.

When counter CNT counts up to 3, relay CN
The logical state of T10 is inactive, and the mask release flag F is set to 1~.

As a result, the masked state of the relay 3 is released. In other words, relay 3 is read as an interrupt input.

Then, the υ1-inclusive processing program corresponding to the stone from which the flowmeter outputs an output is started.

In response to this activation, for example, P I D 1ill DO
O12: is carried out, and the water injection into the tank is controlled at high speed and in a finely tuned manner, and the full water level is adjusted with high precision.

this? If control is performed to reduce the water injection S per unit time in the J-input process 1, more precise control becomes possible in combination with high-speed processing using interrupts.

In this way, since the interrupt controller 3 is used, the output of the flowmeter can be used for both interrupt input and non-interrupt input, and the interrupt input and non-interrupt input are prepared separately. There will be no need to do so.

As is clear from the above application 1 series, in the interrupt controller 1-roller according to the present invention, even when the interrupt input is masked, the input is IF, ! It can be used effectively without being wasted, and can be flexibly adapted to the characteristics of the control system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an interrupt controller according to an embodiment of the present invention, Fig. 2 is a block diagram showing a programmable controller to which the invention is applied, and Fig. 3 is a relay ladder diagram showing a user program. It is. 1...Microcomputer 3...Interrupt controller 31...Selector 33...Control 60 circuit 34...Bright A quality encoder 35...Selection circuit 36.37...Mask register 38...・Three v1-included request registers...Input port a...Input data bus b...Data bus C...Output data bus d to which mask data is sent
...Interrupt request signal line e...Input data path 9 including interrupt input...Output line 11 of masked bits...Output line k of non-masked bits...Data of interrupt cause data Bus Tokumi゛ [Applicant: Tateishi Electric Low Co., Ltd.

Claims (1)

[Claims] (1) A mask that stores mask data sent to the data bus by a microcomputer that processes input data carried on a data bus and performs predetermined interrupt processing in response to an interrupt request signal input to an interrupt port. a register; an interrupt request register that extracts m bits from the input data to be placed on the data bus based on the contents of the mask register and stores the m bits as an interrupt input; and stores the m bits in the interrupt request register. The partial bit interrupt input is divided into masked bits and non-masked bits based on the contents of the mask register, the masked bits are sent to the data bus as part of the input data, and the non-masked bits are sent to the data bus as part of the input data. An interrupt controller comprising: a control unit that issues the interrupt request signal to a microcomputer and sends interrupt cause data to the data bus as input data.