JPS63196903A - Programmable controller - Google Patents

Abstract

PURPOSE:To correctly perform the processing in accordance with prescribed procedures and to miniaturize a device at low cost by discriminating whether each instruction has complete input parameters and is executable or not at the time of reading the instruction and distributing and executing only executable instructions. CONSTITUTION:An input parameter number 35 and a transmission address 37 which is the address of another instruction which inputs output parameters are designated in the instruction in each step of a program, and an active counter 36 which counts the number of times of memory read is provided. The execution of each instruction is divided among arithmetic units 4a-4e, and the address 37 is taken out after the execution of the instruction, and an instruction is read out from an instruction memory 2 in accordance with this address. The value obtained by adding one to contents of the counter 36 of this read instruction is compared with the parameter number 35, and the instruction is executed if they coincide with each other, but one is added to contents of the counter 36 and the instruction is returned to the memory 2 if they do not coincide with each other. Thus, each instruction is executed after required input parameters are completed, and instructions are executed in accordance with correct prescribed procedures.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a programmable controller using a problem-oriented language (CPOL language) used in monitoring and controlling general industrial equipment.

(Prior art) A case where a program created using a problem-oriented language (hereinafter referred to as a POL program) is stored in the instruction memory of a program controller and executed.

One arithmetic unit built into the program controller sequentially reads out the instructions of the stored POL program one step at a time in ascending order of memory address, decodes each instruction code with an interpreter, and sequentially executes a predetermined process corresponding to that instruction. Execute.

Each instruction generally specifies an address in memory where input parameters are stored and an address where output parameters are to be stored, and the arithmetic unit reads the input parameters in memory and performs a predetermined operation. and stores the calculation result at the specified memory address as an output parameter.

One POL program is executed by sequentially repeating such processing.

(Problems to be Solved by the Invention) Incidentally, in recent years, the control contents of program controllers have become more complex, and there has been a demand for faster processing.

However, in the conventional POL program processing method, one arithmetic unit repeatedly decodes and executes instructions in sequence as described above, so the overall processing time increases in proportion to the number of steps in the POL program. Therefore, in order to achieve higher speeds, it is necessary to use a faster execution speed arithmetic unit or to divide the POL program into certain processing units and execute them on multiple programmable controllers. There were problems in that the cost increased and the scale of the system increased.

Also, when split processing is executed by multiple program controllers, the processing results of one process are often used in another process. A device for transferring programs to other program controllers is required, further increasing the scale of the system.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a programmable controller that can be configured at low cost and small in size and can perform high-speed processing.

[Structure of the invention] (Means to solve the problem) For this reason, the present invention includes a plurality of arithmetic units.

and a distributing unit that distributes the instructions of each step read from the instruction memory to those arithmetic units, while the instruction of each step has the number of input parameters of the instruction and the number of input parameters of the instruction read from the instruction memory. The configuration includes an active counter for counting the number of times the instruction has been executed, and a transmission address indicating the memory address of another instruction whose input parameter is the output parameter of the instruction. If there are multiple input parameters, the active counter is counted up and the rewritten instruction is stored in the original memory address, and the input parameters of the read instruction are compared with the active counter. , determines whether or not the instruction can be executed, executes each instruction determined to be executable by multiple arithmetic operations, and after execution of the processing, retrieves the transfer address of each instruction and sequentially reads it from the instruction memory according to the transfer address. Each instruction is read and the above processing is repeated.

(Operation) Since a plurality of instructions are processed in parallel by a plurality of arithmetic units, the processing speed is increased, and the next instruction is read out according to the transmitted address.

When the number of input parameters is multiple, by counting up the active counter of the instruction read from the instruction memory and returning it to the original address, the next time the instruction is read, the input parameters will be stored as data. Since it can be determined whether all the information is stored in memory, processing can be performed reliably according to a predetermined procedure.

(Example) Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 1 is a block diagram of a program controller according to an embodiment of the present invention. In the figure, an addressing unit 1 has a built-in FIFO buffer for storing address data, and sequentially outputs the stored address data to an instruction memory 2.

This indicates a memory address. The instruction memory 2 is a memory in which a POL program is stored, and the distribution unit 3 sequentially reads instructions at the address specified by the addressing unit 1 from the instruction memory 2, and distributes each instruction to the calculation units 48 to 4e. . Each of the calculation units 48 to 4e.

It has a built-in interpreter and executes predetermined processing according to each instruction, and the data memory 5 is a memory in which input parameters and output parameters for the processing are stored. The OR circuit 6 outputs a signal indicating the end of program execution.

Next, the operation of this embodiment will be described, taking as an example a case where arithmetic processing as shown in the control block diagram of FIG. 2 is executed. In the same figure, 11 to 25
indicates each arithmetic processing block of the POL program, and the symbols within the blocks are instruction codes. RO~R35
indicates the address of the data memory 5, and the data at each address becomes the input parameter or output parameter of each process 11-25.

For example, the process 11 performs an arithmetic operation called AIC based on the input parameter stored at address RO of the data memory 5, and stores the output parameter as the result of the operation at address RIO.

Also, from this figure, for example, process 11.12 and process 13.1
4 can be executed first, and process 15 is process 1.
It can be seen that it cannot be executed until all steps 1 to 14 have been executed because the input parameters are not available.

FIG. 3 shows the initial state of a program for performing the arithmetic processing shown in FIG.
is stored in In the figure, an address 31 is an address in the instruction memory 2 that indicates the storage location of each instruction, an instruction code 32 indicates the type of operation, and an input parameter address 33 indicates input parameter data necessary for the operation. This is an address in the memory 5, and the output parameter address is the address of the output parameter in which the calculation result is stored.

The number of input parameters 35 indicates the number of input parameters, and the active counter 36 is for counting the number of times an instruction is read from the instruction memory 2.The initial value is set to 0, and the active counter 36 is for counting the number of times an instruction is read from the instruction memory 2. It can be rewritten as necessary. The transmission address 37 indicates the storage address in the instruction memory 2 of another instruction whose operation result is used as an input parameter in each instruction.However, in the case of the rsTARTJ instruction, it is the instruction to be executed first. Indicates the storage address.

FIG. 4 shows addressing unit 1. The operation of the instruction memory 2 and the distribution unit 3 is shown.

When the addressing unit 1 is activated by the start signal a, it first outputs the address "000" to the instruction memory 2. Instruction memory 2 outputs the instruction stored at address r000J to distribution unit 3.

As a result, the first instruction, in this case the rsTARTJ instruction, is read out (FIG. 4, process 41).

The distribution unit 3 inputs the command and turns on the busy signal. Then active counter 3 in that instruction
6 is extracted, the value is incremented by +1 (process 42), and the +1 value of the active counter is compared with the number of input parameters 35 (process 43). In the start command, the active counter is "0" and the number of input parameters is "1", so
In this process, both match. In this case (processing 43
Y), the active counter that has counted up is set to ``0''.
'' and stores it at a predetermined original address in the instruction memory 2 (processing 44).

While the arithmetic units 48 to 4e are operating, the one distribution unit 3 to which the busy signal C is output next searches for an idle arithmetic unit to which the busy signal C is not output (45), and selects one of them. Then, the command received from the command memory 2 is transferred (process 46). Normally, in the initial state when the rsTARTJ instruction is executed, everything is in an idle state, so here it is assumed that the instruction is transferred to the arithmetic unit 4a.

FIG. 5 shows the operation when the arithmetic units 48 to 4e receive the above instruction. When the instruction is transferred from the distribution unit 3 (process 51), turn on the busy signal C (process 52), determine whether it is an rENDJ instruction (process 53), if it is not an rENDJ instruction (N in process 53),
Predetermined arithmetic processing is executed according to the instruction code of the instruction (processing 54).Since this is an rsTARTJ instruction, no arithmetic processing is performed.

Next, the transfer address of the instruction is sequentially transferred to the addressing unit 1 via the address bus n.

In the start command shown in Figure 3, roolJ, r008
J.

Four addresses, roloJ and ro1, are transferred (process 55).

Thereafter, the busy signal C is turned off (56), and one command processing is completed.

On the other hand, when the addressing unit l stores the transferred address in the internal FIFO buffer (FIG. 4, process 47), if there is a stored transferred address (Y in process 48), the busy signal is turned off. Each time, the address is sequentially output to the instruction memory 2. This results in
A corresponding instruction is read from the instruction memory 2, and the same process as described above is repeated (process 41 to process 48).

Through this process, as shown in FIG.
After the instruction is executed, the instruction rAIcJ of the transfer address rooIJ transferred to the addressing unit 1 is read out, and the instruction is executed in the arithmetic unit 4a, for example, and after the execution, the transfer address r002J is transferred to the addressing unit 1. Then, the FIF of addressing unit 1
Similarly, the instruction "^ICJ" at address ro08J is read from O, and executed by the arithmetic unit 4b, and the transfer address rOQ9J is transferred. In this way, the instruction corresponding to the transfer address is shared among the arithmetic units 48 to 4e. They will be executed in parallel and sequentially.

Here, when the instruction rANDJ at address r003J is read out for the first time, the number of input parameters 35 is "2", so the active counter 3 is incremented by 1 in process 43.
6 and the number of input parameters do not match. In this case, +
The active counter 36 that has been set to 1 is stored in the original address ro03J of the instruction memory 2 (49), and the instruction is not executed. As shown in FIG. 6, address ro03J includes instructions rt, vcn for
: is specified as the twice-transmitted address.

Therefore, when the instruction at address r003J is read out for the second time, the active counter 36 has been incremented by 1 the previous time, so it becomes +2, and in process 43, the two match.
At this time, the instruction rADDJ is executed.

By the way, the above instruction rADDJ corresponds to process 15 in FIG. 2. As mentioned above, process 15 can only be executed after all processes 11 to 14 have been executed.
Since the instruction rLVcJ corresponds to processes 12 and 14, this instruction rADDJ will be executed after both processes 12 and 14 have been executed.

This is the same for the instruction rADDJ in process 21, and although it is not shown in Figure 2, even instructions with three or more input parameters are executed after all input parameters are collected. It turns out.

When addressing unit 1 runs out of transfer addresses to be output in the FIFO buffer (N in process 48),
Finish the action. On the other hand, in the program shown in FIG. 3, the rENDJ instruction is executed at the end. When the arithmetic units 1 to 4a to 4e receive the rENDJ command, they output an end signal d. This end signal d is output from the OR circuit 6, indicating the end of the program.

As described above, in this embodiment, in the instruction for each chip of the program, the number of input programs 35 and the transmission address 37 which is the address of another instruction to which the output parameter of the instruction is input are specified. , an active counter 36 is provided to count the number of times the instruction is read from the memory. In addition, a plurality of calculation units 4
8 to 4e are arranged, and each instruction is sent to each arithmetic unit 48 to 4.
After each instruction is executed, the transfer address is taken out, the instructions are read from the instruction memory 2 in the order of the address, and the active counter of the read instruction is incremented by 1 and the number of input parameters is compared. When the two match, the instruction is executed, while when they do not match, the active counter is incremented by one and the instruction is returned to the instruction memory 2. As a result, each command is executed after the necessary input parameters are collected, and the command is processed according to the correct predetermined procedure.

In this way, each process is divided among a plurality of arithmetic units and executed in parallel, so that the processing time of the entire program is shortened. In this case, one distribution unit 3 is installed in the conventional program controller, and the number of calculation units is increased to multiple.

Unlike the case where multiple program controllers are installed, the cost and size are not high and large. Also,
The arithmetic units 48 to 4e are not high-speed ones, but conventional ones can be used.

In this embodiment, five arithmetic units 48 to 4e are provided, but it goes without saying that any number of arithmetic units may be used.

For example, when creating a program that performs the processing shown in Figure 2 even when there is only one arithmetic unit,
Conventionally, processing 15 had to be arranged after processing 12 and 14 according to the data flow, but as shown in FIG. 3, the processing can be performed correctly even if the arrangement is forward or backward.

In addition, the addressing unit and distribution unit are LSI
The processor used in the arithmetic unit I- has recently become inexpensive, and by using a plurality of such processors, the cost can be reduced.

[Effects of the Invention] As described above, according to the present invention, multiple instructions are processed in parallel by multiple arithmetic units, so high-speed processing is possible. Each instruction can be read from the instruction memory by specifying a transmission address, which is the address of another instruction that inputs the output parameters of the instruction, and by providing an active counter that counts the number of times the instruction is read from the memory. When the instruction is executed, it can be determined whether the instruction is executable with all the input parameters, and only executable instructions are distributed to the processing units for execution, so that the instructions are processed correctly according to the predetermined steps. . In addition, since the device configuration includes a plurality of arithmetic units and only one distribution unit I-, the device can be configured in a small size and at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a programmable controller according to an embodiment of the present invention, FIG. 2 is a block configuration diagram showing an example of the arithmetic processing performed in FIG. 1, and FIG. An explanatory diagram showing an example of a program for carrying out the
FIG. 4 is a flow chart showing the operation of reading instructions and distributing them to the arithmetic units, FIG. 5 is a flow chart showing the operation of the arithmetic units, and FIG. 6 is an explanatory diagram showing the execution procedure of the arithmetic processing of FIG. 2. 1...Addressing unit, 2...Instruction memory,
3... Distribution unit, 4a-4e... Arithmetic unit. 5...Data memory, 32...Instruction code, 33.
...Input parameter address, 34...Output parameter address, 35...Number of input parameters, 36...
Active counter, 37...Transmission address. Agent Patent Attorney Crest 1) Makoto □Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] Each instruction of the problem-oriented language is defined as an instruction code for executing various arithmetic operations, an input parameter address and an output parameter address for storing input parameters and output parameters in these arithmetic operations, and the number of input parameters.
A program that is composed of an active counter that counts the number of times an instruction is read from memory, and a transmission address that indicates the address of another instruction whose input parameter is the output parameter of that instruction, and that is created using that instruction. an addressing unit that reads out each instruction from the instruction memory according to the transmission address; and an execution determination unit that determines whether or not the instruction can be executed based on the number of input parameters and the active counter of each read instruction. means for rewriting an active counter for adding 1 to the active counter and storing the instruction at the original address of the instruction memory when it is determined that the instruction cannot be executed; , a plurality of arithmetic units that transfer the transmission address of the executed instruction to the addressing unit, a data memory that stores input parameters and output parameters in arithmetic processing of the arithmetic units, and a judgment that the execution is executable by the execution judgment means. a distribution unit that distributes each instruction issued to the plurality of arithmetic units and instructs the addressing unit to execute a process of reading an instruction from the instruction memory according to the next transmission address, and processes the plurality of instructions in parallel. A programmable controller characterized by: