JPH03191459A - Interruption response processor - Google Patents

Abstract

PURPOSE:To grasp the interruption factors of a device having plural interruption factors by reading out a corresponding vector number in accordance with an interruption request signal and selecting and executing a processing program. CONSTITUTION:When an interruption request signal is outputted from a generating means 1, a reading means 3 reads out the corresponding 1st vector number from a storage means 2 in accordance with the level difference of the interruption request signal. A processing control means 4 requests the specification of a vector number to an interruption generating means 1 based upon the 1st vector number. The means 4 retrieves a required interruption processing program based upon the 2nd vector number outputted from the means 1 and executes interruption processing in accordance with the program. Thereby, the data of one vector number requiring the interruption processing is obtained from the means 1 and the required interruption processing is surely selected and executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to interrupt processing of a multi-CPU system,
In particular, the present invention relates to an interrupt response processing device after an interrupt signal is input.

〔overview〕

In a so-called multi-CPU system consisting of multiple processors, when an interrupt request occurs to the processor in the middle of execution of processing by the - processor, the interrupt request signal is output to the other processors, and the signal possessed by this interrupt signal is output. A so-called auto-vector method is adopted in which a corresponding vector number is read out from the level difference, and other processors perform corresponding interrupt processing based on the vector number read out using this method.

However, in auto-vector interrupt response processing, −
In the case of a processor with multiple interrupt sources, it is difficult to integrate such a processor into the system unless you use a method such as assigning an interrupt request signal to each interrupt source. Unable to connect.

In the present invention, depending on whether or not the processor to which the interrupt request signal is output has multiple interrupt sources, for example, if the interrupt request signal is from a processor having multiple interrupt sources, the vector number selected by the processor is set to By using this as a vector number request signal to the processor that outputs the vector number, it is possible to know the cause of the interrupt of such a processor. Further, by processing in this way, even a processor having multiple interrupt factors can be connected to the system.

[Conventional technology]

With the development of microprocessors, multi-CPU systems have been put into practical use, in which not only one CPU performs control and processing, but also multiple processors simultaneously perform control and processing. In such a system, each processor including the user device individually executes a control program or a processing program, and when a processor or a user device requests processing to the CPU in the middle of executing the process according to the program, For example, the target CPU via the VME bus.
It outputs an interrupt signal to the CPU and causes other CPUs to perform the desired processing.

Conventionally, an autovector method has been adopted for response processing to the above-mentioned interrupt request signal in order to efficiently perform the interrupt response processing in a short time. In other words, interrupt request signals with different signal levels are output to the CPtJ in order to determine the processor that outputs the interrupt signal, and the CPU reads the corresponding vector number from the table based on this signal level difference and issues the corresponding interrupt. It performs processing.

[Problems to be Solved by the Invention] In the above auto-vector type interrupt response processing device, -
Since only a negative vector number can be obtained for an interrupt request signal of ), or the CPU cannot connect to the system unless it has a means to know the interrupt cause.

Therefore, the problem can be solved if it is possible to know by some means which interrupt request has been made to a processor having multiple interrupt factors.

An object of the present invention is to make it possible to know the interrupt factor of a device based on a negative interrupt request signal from a device having a plurality of interrupt factors.

[Means to solve the problem]

The means of the present invention are as follows.

The interrupt generating means 1 (see the block diagram of the present invention in FIG. 1, the same shall apply hereinafter) is a processor or a user device, and for example, interrupt generation means 1 (see the block diagram of the present invention in FIG. 1, the same shall apply hereinafter) is a processor or a user device, and for example, interrupt generation means 1 (see the block diagram of the present invention in FIG. 1) is a processor or a user device. Has basic interrupt sources.

The storage means 2 stores first vector numbers corresponding to, for example, differences in signal levels of the interrupt request signals output from the interrupt generation means 1.

The vector number reading means 3 is the interrupt ordering means 1.
The corresponding first vector number is read from the storage means 2 in accordance with the interrupt request signal output from the storage means 2.

The processing control means 4 receives a second vector number for necessary interrupt processing from the interrupt generation means 1 based on the first vector number read out by the reading means 3, that is, specifically among a plurality of interrupt causes. A vector number for selecting a processing program for executing the second interrupt processing is read out, and an interrupt processing program is selected and executed according to the second vector number.

[For production]

The operation of the means of the invention is as follows.

When an interrupt request signal is output from the interrupt generating means 1, which has a plurality of interrupt sources and is connected to a processor or a user device via a VME bus, for example, the reading means 3 detects, for example, the difference in signal level between the interrupt request signals. Accordingly, the corresponding first vector number in the storage means 2 is read out. For example, this vector number allows the corresponding interrupt processing program to be read directly from this first vector number for an interrupt request signal output from an interrupt generating means that has only a negative interrupt request factor. . The processing control means 4 issues a vector number instruction request to the interrupt generation means 1 from the first vector number, and controls the processing based on the second vector number output from the interrupt generation means 1 in accordance with the instruction request. Means 4
The system searches for a desired interrupt processing program and executes interrupt processing according to the program.

Therefore, the data of the - vector number that requires interrupt processing can be obtained from the interrupt generating means 1 having a plurality of interrupt causes, and the necessary interrupt processing can be reliably selected and executed.

〔Example〕

One embodiment will be described below with reference to FIG.

FIG. 2 is a block diagram of a computer system including an interrupt response processing device according to one embodiment. In the same figure, C
The PU 6 performs control according to a system program stored in a ROM 7 that is part of the memory 5, and performs interrupt response processing between a vector number table 9 connected to the CPU 6 and an interrupt response processing circuit 8 when an interrupt signal (to be described later) is input. conduct.

Incidentally, a vector number table 9 is also provided in a part of the memory 5.

Further, an interrupt generating device 10 is connected to the CPU 6 via the VME bus. The interrupt generating device 10 is, for example, a processor having multiple interrupt processing request factors such as power abnormality detection and timer processing, or a user device. , or a device that performs processing such as DMA transfer. This interrupt generating device 10 outputs an interrupt request signal (IRQ) to the CPU 6 when interrupt processing is required. In addition, as described in detail later, an interrupt acknowledge signal (I
ACK) is supplied from an interrupt response processing circuit 8, which will be described later, outputs corresponding vector number (DB) data to the CPU 6.

The vector number table 9 stores a plurality of vector numbers, and stores the start address of an interrupt processing program corresponding to each vector number or address data for outputting an interrupt acknowledge signal. The vector numbers in this vector number table are read out by a control signal output from the CPU 6.

I10 data and a function code (FC) are input to the interrupt response processing circuit 8 from the CPU 6. Specifically, the I10 data is data obtained by decoding the address data output from the CPU 6 by the address decoder 11. Further, when the interrupt response processing circuit 8 receives a function code, it outputs an instruction signal (AVCE) to cause the CPU 6 to execute autovector processing.

In the interrupt response processing device having the above configuration, the processing operation when an interrupt request signal is output from the interrupt generating device 10 to the CPU 6 will be explained. First, a case will be described in which the interrupt generating device 10 is a device in which there are only negative interrupt factors.

In this case, the interrupt generating device 10 sends an interrupt signal having a predetermined voltage level to the CP via the VME bus.
Output to U6. When the CPU 6 receives this signal, it outputs a function code to the interrupt response processing circuit 8 to obtain the vector number. When this function code is input, the interrupt response processing circuit 8 outputs an autovector instruction signal to the CPU 6, and thereafter requests the CPU 6 to search for a vector number using the autovector method. CPU6
In response to the above request, searches the vector number in the vector number table 9 from the voltage level of the interrupt signal input to the CPU 6, reads the corresponding vector number, and executes a predetermined interrupt processing program from this vector number.

Next, a case will be described in which the interrupt generating device 10 is a device having two or more interrupt sources.

In this case as well, when the CPU 6 receives an interrupt signal having a predetermined voltage level from the interrupt generating device 10 via the VME bus, it outputs a function code to the interrupt response processing circuit 8 in the same manner as described above, and processes the interrupt response. An autovector instruction signal is obtained from the circuit 8, and the corresponding vector number is read from the vector number table 9 based on the voltage level of the interrupt signal. The vector number thus obtained is address data for outputting an interrupt acknowledge signal, and the CPU 6 outputs this data to the address decoder 11.

The address decoder 11 sends decoded data corresponding to the input data to the interrupt response processing circuit 8, and when this decoded data is input, the interrupt response processing circuit 8 outputs an interrupt acknowledge/noji signal to the interrupt generating device 10. At this time, the CPU 6 simultaneously outputs data 8 at a predetermined address level based on the signal level of the input interrupt request signal. The data at address level A is determined and outputted by the CPU 6 from the signal level of the interrupt signal. Then, the interrupt acknowledge signal is input to the interrupt generating device 10 that has output the interrupt request signal. The interrupt generating device 10 to which the interrupt acknowledge signal is input outputs to the CPU 6 the data of the vector number that requires interrupt processing that matches the level of data A among the plurality of interrupt causes. CPU
6 executes interrupt processing in accordance with this vector number when data of this vector number is input.

Therefore, the vector number of the process that specifically requires interrupt processing when the interrupt generating device 10 outputs an interrupt request signal among the plurality of interrupt factors possessed by the interrupt generating device 10 is outputted to the CPU 6, so that it is accurate. In addition, the CPU 6 can determine the interrupt processing of the interrupt generating device and execute the corresponding interrupt processing.

(Effects of the Invention) According to the present invention, even in a device having a plurality of interrupt causes, the corresponding interrupt process can be determined based on a negative interrupt request signal, and the interrupt process required by the device can be reliably executed.

Further, for a device having only a negative interrupt factor, interrupt response processing can be performed in accordance with the conventional interrupt signal using the auto-vector method.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a system block diagram of an interrupt response processing device according to an embodiment. ■...Interrupt generation means, 2...Storage means, 3...Reading means, 4...Processing control means.

Claims (1)

[Claims] an interrupt generating means having a plurality of interrupt request sources;
storage means for storing a first vector number corresponding to the interrupt request signal output from the interrupt generation means; reading means for reading out the first vector number stored in the storage means in accordance with the interrupt request signal; processing control means for reading a second vector number corresponding to a necessary interrupt processing from the interrupt generation means based on the first vector number read by the reading means and executing the interrupt processing according to the second vector number; An interrupt response processing device comprising: