JPH0495135A - External transmission signal control system - Google Patents

Abstract

PURPOSE:To increase the number of degrees of freedom of connection between a CPU and external transmission signals without increasing the number of input ports of external transmission signals of a CPU by performing the processing different by the value of a corresponding input port control code storage part. CONSTITUTION:A processor is provided with a value storage part, an input port control code storage part, and an external transmission signal control part correspondingly to each input port, and each external transmission signal control part refers to the value of the input port control code storage part to update handling of the external transmission signal inputted to the input port. That is, the value of the external transmission signal is written in the corresponding value storage part, and external transmission signals are taken as sequential object signals at the time of specific operation of the processor, and a context dependent interrupt factor is generated when the external transmission signal goes to a prescribed value, and a context independent interrupt factor is generated when the external transmission signal goes to a prescribed value. Thus, the number of degrees of freedom of connection between the processor and external transmission signals is increased.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to increase the degree of freedom in connection between the processor and externally transmitted signals with respect to the externally transmitted signal control system for the processor. Value storage.

An input port control code storage unit and an external transmission signal control unit are provided, and each external transmission signal control unit (a) stores the corresponding external transmission signal when the value of the input port control code belongs to the first value set; (b) The value of the input port control code is the second
(c) If the value of the input port control code belongs to the third value set, the corresponding external signal is the signal to be serialized during a specific operation of the processor. Generate a context-dependent interrupt factor when the outgoing signal reaches a predetermined value, and (d) if the value of the input port control code belongs to a fourth value set, generate a context-dependent interrupt factor when the corresponding external outgoing signal reaches the predetermined value. Configured to generate independent interrupt sources.

[Industrial Application Field] The present invention relates to a method for controlling processor operation in response to an externally transmitted signal in a processor to which an externally transmitted signal transmitted from a hardware unit external to the processor can be connected. The purpose is to increase freedom.

A processor equipped with basic instructions (for example, a central processing unit) and an external hardware unit such as a coprocessor for specific processing that can be connected to it are prepared, and external hardware units that can be connected to the processor depending on the purpose of use are prepared. By selecting the unit, you can have a flexible hardware configuration with high cost performance depending on the purpose of use.

This method is often used, especially in the field of microprocessors.

[Prior Art] Conventionally, for large-sized computers, buyers did not purchase only a single central processing unit, but rather a system consisting of a central processing unit and various external devices. In this case, the purchaser purchases only the central processing unit and adds various external devices to it to construct a computer system. In conventional microprocessors, the types of externally transmitted signals connected to externally transmitted signal input ports (input ports) are fixed for each input port.

[Problem to be Solved by the Invention] Therefore, when trying to construct a hardware system configuration consisting of There were cases where there was a shortage.

Additionally, in order to provide a wide range of connection configurations between the central processing unit and external hardware units, it becomes necessary to provide a sufficient number of external input signal ports for each type of externally transmitted signal; This is undesirable because it increases the number of pins in the LSL package of the device.

The present invention was created in view of this point, and an object of the present invention is to provide an externally transmitted signal control method that can increase the degree of freedom of connection between the input port of a processor and an externally transmitted signal. There is.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. The present invention relates to an external transmission signal control method in a processor having one or more input ports for inputting external transmission signals.

The processor includes a value storage section that is provided for each input port and can be referenced from the program, an input port control code storage section that is provided for each input port and can be rewritten by the program, and an external control code storage section that is provided for each input port and can be referenced by the program. and a transmission signal control section.

(a) If the value of the corresponding input port control code storage belongs to the first value set, the external transmission signal control section only performs the process of writing the value of the corresponding external transmission signal into the corresponding value storage. (c) If the value of the corresponding input port control code storage unit belongs to the second value set, the corresponding externally transmitted signal is set as a signal to be serialized during a specific operation of the processor; If the value of the input port control code storage unit to be processed belongs to the third value set, a context-dependent interrupt factor signal is generated when the corresponding externally transmitted signal reaches a predetermined value, and (d) responds. When the value of the input port control code storage unit belongs to the fourth value set, the system is configured to generate a context-independent interrupt factor signal when the corresponding externally transmitted signal reaches a predetermined value. .

[Effect]

The i-th external transmission signal control section refers to the value of the i-th input port control code storage section and changes the handling of the external transmission signal input to the i-th input port.

When the value of the i-th input port control code storage unit belongs to the first value set, the i-th external transmission signal control unit controls the value of the external transmission signal input to the i-th input port. Only the process of writing to the i-th value storage unit is performed.

When the value of the i-th input port control code storage unit belongs to the second value set, the i-th external transmission signal control unit transmits the external transmission signal input to the i-th input port to the processor. be serialized during specific operations. Serialization of a specific operation of the processor means that the start of a specific operation of the processor is made to wait until the corresponding externally transmitted signal reaches a specific value.

When the value of the i-th input port control code storage unit belongs to the third value set, the i-th external transmission signal control unit specifies that the external transmission signal input to the i-th input port A context-dependent interrupt factor signal is generated when the value of . A context-dependent interrupt is an interrupt that occurs at least in synchronization with a context.

A context-dependent interrupt is an interrupt that occurs after execution of the instruction that started the process that caused the interrupt, but before any other interrupt occurs (without context switching).

When the value of the i-th input port control code storage unit belongs to the fourth value set, the i-th external transmission signal control unit specifies that the external transmission signal input to the i-th input port A context-independent interrupt factor signal is generated when the value of . A context-independent interrupt is an interrupt that occurs asynchronously with the instruction execution of the processor.

The processor program can refer to the value storage section and can also rewrite the values in the input port control code storage section.

[Embodiment] FIG. 2 is a diagram showing an example of the hardware configuration of an embodiment of the present invention. In the figure, #0 to #7 are programmable externally transmitted signal input ports, 100 is a CPU, 110 is an externally transmitted signal value register, 120 is an externally transmitted signal operation regulation register, 130 is a coprocessor busy serialization mask, and 200 is a Main memory, 300 is a floating point hectare.
A coprocessor, 400 indicates an input/output coprocessor, and 500 indicates a system bus.

CP Uloo has input ports #0 to #7. External transmission signal value register 110, external transmission signal operation regulation register 120. Coprocessor busy serialization mask 130
etc. Input port #X of CPU100 (
X=0.1. . . , 7) is 1 bit wide.

The system bus 500 includes CPUs 100 . Main storage device 200. A floating point hector coprocessor 300, an input/output coprocessor 400, and the like are connected.

CP [Jlooo's input ports are connected to the signals shown in the figure.

The external transmission signal value register 110 is an 8-bit long register, and bit #X indicates the value of the external transmission signal connected to input port #X. The external transmission signal value register 110 can be referenced from the program.

FIG. 3 is a diagram showing an example of the configuration of an external transmission signal operation regulation register. In the same figure, ESCTLO or ESCT
L7 indicates an input port control code. In addition, ESCTL
is External Signal Contr.

It is an abbreviation of l.

Externally transmitted signal operation regulation register 120 is a 32-bit long register that holds a 4-bit long input port control code for each input port. That is, input port #X
ESCTLX is assigned to (X=0.1...7). The program can rewrite the external transmission signal operation regulation register 120.

FIG. 4 is a diagram illustrating the handling of the ESCTL value and the corresponding input port signal.

As shown in the figure, when ESCTL=0000 to 0101, the CPU displays only the value in the external transmission signal register.

When ESCTL=0110, the CPU handles the connection signal as a level signal, and uses it as a signal to be serialized during CPU interrupt operation. While this signal is 1, the CPU does not generate an interrupt.

When ESCTL=0111, the CPU handles the connection signal as a pulse signal, and generates a context-dependent interrupt factor when the connection signal becomes 1.

When ESCTL=IXYZ, the CPU handles the connection signal as a pulse signal and generates a context-independent interrupt factor of priority level XYZ when the connection signal becomes 1.

The coprocessor busy serialization mask 130 will now be described. A plurality of coprocessors can be connected to the CPU 100. The coprocessor busy serialization mask 130 specifies whether to serialize CPU operations by waiting until the coprocessor busy signal becomes 0. A program can rewrite the coprocessor busy serialization mask 130. This allows the program to set the coprocessor busy serialization mask to 1 (
The busy signal of that coprocessor is targeted for serialization)
shall be. This increases the degree of freedom in connecting coprocessors. When debugging, set the coprocessor busy serialization mask for that coprocessor to 1, and
By setting V, 5YNC=1 (a flag that serializes the CPU operation each time an instruction is executed), the coprocessor operation can be executed synchronously with the CPU operation. In addition, PEV stands for Processing Environme.
nt, which is the P of Fujitsu's M series computer.
This corresponds to the upper word of SW.

ESCT for each input port in the embodiment of FIG. 2
The value of L and the connection signal will be explained.

For input port #0, set ESCTL=0110,
Connect the main storage device busy signal to input port #0.

The main memory device busy signal indicates that the main memory device is executing main memory access from the CPU.
It is subject to serialization during interrupt operation of the PU. A main memory busy signal of 0 indicates that all main memory accesses have been completed based on requests from the CPU, and a main memory busy signal of 1 indicates that main memory accesses based on requests from the CPU are being executed. In response to a store request from the CPU, the main memory device performs the process up to the detection of a program exception synchronously, and the subsequent writing of data to memory is performed by the CPU.
is executed asynchronously.

In this asynchronous execution part, context-dependent interrupt factors for memory failures may be detected.

For input port #1, set ESCTL=0111,
A context-dependent interrupt factor generation signal for a memory failure detected in connection with an access request from the CPU is connected to input port #l.

This signal can be 1 only while the main memory busy signal is 1.

For input port #2, ESCTL is set to 0110 or 0000, and the busy signal of the floating point vector coprocessor is connected to input port #2. A floating point vector coprocessor busy signal of 1 indicates that the floating point vector coprocessor is executing a process requested by the CPU. If you want to treat interrupts from a floating-point vector coprocessor as context-dependent interrupts,
The ESCTL for this signal is 0110 in binary. If this interrupt is to be a context-independent interrupt, the ESCTL for this signal is set to 0000 in binary. When running a program in which multiple processes using a vector coprocessor are executed simultaneously in time slices, the coprocessor interrupt is set as a context-dependent interrupt, and the program is executed only when there is only one process using the vector coprocessor. environment, coprocessor interrupts are context-independent interrupts.

For input port #3, set ESCTL=0000,
Connect the floating point vector coprocessor's posted unfinished signal to input port #3. A post mechanism exists as a mechanism for ensuring the completion of a specific main memory access of a floating-point vector coprocessor. This post unfinished signal remains 1 only until all main memory accesses started by the floating point vector coprocessor before the post coprocessor instruction issued by the CPU are completed. A specific main memory access completion guarantee procedure for a floating point vector coprocessor using a post mechanism is as follows.

■ Memory for floating-point vector coprocessors
Issue an access command (multiple access commands may exist).

■ A post coprocessor instruction is issued by the CPU.

■ During this time, any instructions to the CPU and floating point vector coprocessor are issued.

(2) Wait for the value of the post unfinished signal to become 0 at the time when the completion of the main memory access by the floating point vector coprocessor in (2) should be guaranteed.

■ At this time, it is guaranteed that the memory access of the floating point vector coprocessor in ■ has been completed.

For input port #4, ESCTL is set to 0111 or 1010, and the interrupt signal of the floating point vector coprocessor is connected to input port #4. This signal becomes 1 when an interrupt factor is detected while the floating-point vector coprocessor is executing processing. When making a floating point vector coprocessor interrupt a context-dependent interrupt, set ESCTL to 0111.

Furthermore, if this interrupt is to be a level 2 context-independent interrupt, 1010 is set in ESCTL.

For input port #5, set ESCTL=1011,
Connect the input/output coprocessor interrupt signal to input port #5. Since the input/output coprocessor interrupt signal is treated as a level 3 context-independent interrupt, ESCTL
Set 1011 to .

FIG. 5 is a diagram showing an example of the hardware configuration of the external input signal processing section. In the figure, 110 is an external transmission signal value register, 120 is an external transmission signal operation regulation register, and 14
0 is a decoder, 150 is an input selection section, 160 is a CP
The U control unit 170 indicates a CPU data bus.

The input pin PIN is a pin of an input port. Decoder 1
40, the input port number is #X (X=0.1゜...
, 7), ESCTLX is decoded. The signal from the input pin PIN is input to the input select section 150.
bit X of the external oscillation signal value register 110. The CPTJ control unit 160 includes ESCTLX
The decoding result and the output of bit X of the external oscillation signal value register 110 are input.

The input terminal of the external transmission signal operation regulation register 120 is the CPU
The output side of the external transmission signal operation regulation register 120 is also connected to the CPU data bus 170 . Bit X of external transmission signal value register 110
The output side of is also connected to the CPU data bus 170.

FIG. 6 is a diagram illustrating details of the input select section and the CPU control section. FIG. 6 shows details within the dotted line in FIG. In the same figure, 151 is an AND circuit;
2 is an OR circuit, 161 to 163 are AND circuits, 16
4 indicates a serialization control section, and 165 indicates an interrupt control section.

The signal from the input pin PIN is set to bit X of the external oscillation signal value register via the OR circuit 152 in clock synchronization. When the decoding result of ESCTLX indicates a pulse and the signal on the input pin PIN is 1, 1 is held in bit X of the external oscillation signal value register.

When ESCTLX is 0110 and the value of bit X of the external oscillation signal value register is 1, the AND circuit 161 outputs 1.
Output. The output of the AND circuit 161 is input to the serialization control section 164 as a serialization signal. Serialization control unit 16
Only one portion 4 exists in the CPU0, and is a portion that controls serialization of CPU operations. Specifically, when an interrupt occurs, wait for the operation targeted for serialization at the time of the interrupt to finish.

-PEV, 5YNC= 1? , CPU (7) When sequential execution of instructions is specified by the program, the CPU waits for the completion of the (asynchronous) operation to be serialized before starting execution of the instructions.

etc.

When ESCTLX is 0111 and the value of bit X of the external oscillation signal value register is 1, the AND circuit 162 is 1.
Output. The output of the AND circuit 162 is input to the interrupt control unit 165 as a context-dependent interrupt signal.

The interrupt control unit performs operations such as detecting an interrupt condition, waiting for completion of serialization of CPU operations at the time of an interrupt, and displaying interrupt parameters and changing the environment (changing control registers).

When ESCTLX is 1XYZ and the value of bit X of the external oscillation signal value register is 1, the AND circuit 163 is 1
Output. The output of the AND circuit 163 is at level XYZ
Interrupt controller 1 as a context-independent interrupt signal
65. Although only one context-independent interrupt generation means is shown in the figure, there are actually eight context-independent interrupt generation means.

[Effects of the Invention] As is clear from the above description, according to the present invention, (a) the degree of freedom in connecting the CPU and externally transmitted signals can be increased without increasing the number of input ports for externally transmitted signals of the CPU; It can be increased.

(b) The operation of the CPLI for each externally transmitted signal can be automatically changed in response to changes in the operating environment of the program.

This can produce a remarkable effect.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram showing an example of the hardware configuration of an embodiment of the invention, FIG. 3 is a diagram showing an example of the configuration of an external transmission signal operation regulation register, and FIG. ESCT
A diagram explaining the handling of the value of L and input port signals, Figure 5 is a diagram showing an example of the hardware configuration of the external input signal processing unit, and Figure 6 shows details of the input selection unit and CPU control unit in Figure 5. FIG. #0 to #7: Programmable external transmission signal input port, 100: CPU, 110: External transmission signal value register, 120: External transmission signal operation regulation register, 130: Coprocessor busy Serialization mask, 140... Decoder, 150... Input selection section, 151... AND circuit, 152... OR circuit, 1
60...CPLI control unit, 161 to 163...
AND circuit, 164... serialization control unit, 165...
Interrupt control unit, 170...CPU data bus, 200
. . . Main storage device, 300 . . . Floating point vector coprocessor, 400 . . . Input/output coprocessor, 500
...System bus.

Claims (1)

[Scope of Claim] An externally transmitted signal control method in a processor having one or more input ports for inputting externally transmitted signals, the processor comprising: a value storage unit provided corresponding to each input port and which can be referenced from a program; It is equipped with an input port control code storage section that is provided for each input port and can be rewritten by a program, and an external transmission signal control section that is provided for each input port, and each external transmission signal control section: (a) The value of the corresponding input port control code storage unit is the first
(b) If the value of the corresponding external transmission signal belongs to the value set of the second
(c) if the value of the corresponding input port control code storage unit is the third
(d) If the value of the corresponding input port control code storage unit belongs to the fourth
An externally transmitted signal control method, characterized in that, when the corresponding externally transmitted signal belongs to a value set of , a context-independent interrupt factor signal is generated when the corresponding externally transmitted signal reaches a predetermined value.