JP2968321B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a data processing device having a vector processing mechanism, an operation test of a vector unit is performed in parallel with an operation test of a CPU to shorten the operation test period of the entire data processing device. For the purpose, the vector unit includes a selection circuit for selecting one of the outputs of the CPU and the external device, and a buffer register for storing the output of the selection circuit.

[Industrial applications]

 The present invention relates to a data processing device.

[Conventional technology]

In recent data processing devices called supercomputers, in addition to the conventional CPU, a new processor,
For example, a vector unit or the like is provided. In such a supercomputer, the CPU decodes the instruction, and if the instruction is a vector instruction, sends the instruction to the vector unit. At this time, if the operand of the vector instruction requires data of a general-purpose register or a floating-point register in the CPU, it is also sent to the vector unit.

Conventionally, in the operation test of the supercomputer, the operation test of the vector unit can be performed only after the operation test of the CPU is completed. This is because the operation of a vector instruction can be performed only when the CPU fetches an instruction such as a vector instruction and the like, decodes the instruction, and transfers the instruction to the vector unit. Therefore, since the operation test of the vector unit is performed after the operation of the CPU, the operation test of the entire supercomputer requires a long period of time.

[Problems to be solved by the invention]

The present invention eliminates the above-mentioned disadvantages of the prior art, and provides a data processing apparatus capable of performing an operation test of a vector unit in parallel with a CPU, and thus having a short entire operation test period of the entire data processing system including a vector processing mechanism. The purpose is to do.

[Means for solving the problem]

The data processing apparatus according to the present invention processes a first type of instruction by itself, and transfers a second type of instruction to a first processor and a second type of instruction transferred from the first processor. A second processor for processing the instructions; and an external device for supplying a second type of instruction to the second processor, wherein the second processor selects one of the outputs of the first processor and the external device. And a buffer register for storing the output of the selection circuit.

The data processing device according to the present invention is further configured such that the selection operation of the selection circuit can be controlled by a command from an external device.

[Action]

In the operation test of the second processor, a command for setting the test mode from the external device is sent to the second processor. In the second processor, the selection circuit is switched to select the output of the external device. A second type of operation test instruction is sent from the external device and stored in the buffer register via the selection circuit.

Predetermined processing is performed on the instruction stored in the buffer register.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 FIG. 1 shows the configuration of a data processing device according to the present invention.

In FIG. 1, reference numeral 1 denotes a normal CPU;
The instruction and data stored in the instruction are read, the instruction is decoded, and the execution of the instruction is controlled. A portion 3 surrounded by a dotted line indicates a vector unit. If the instruction decoded by the CPU 1 relates to a vector operation, the vector unit 3 sends the instruction (including the operand) to the CPU 1
And a processor that executes the vector operation.

The service processor (SVP) 4 is an external device that is operated independently. In the present invention, the service processor (SVP) 4 selects an operation mode of the vector unit and supplies a vector instruction in the test mode.

The vector unit 3 has a plurality of selection circuits 6, and the outputs of the CPU 1 and SVP4 are input to each selection circuit 6.

The SVP command control circuit 7 receives a command from SVP4, codes the command, and sends a control signal to each selection circuit 6 based on the result. Each selection circuit 6 selects one of the two inputs from the CPU 1 and SVP 4 according to this control signal and outputs it.

An output of each selection circuit 6 is connected to an instruction buffer 8 for storing a vector instruction and an operand buffer 9 for storing a scalar operand. When the output of the SVP4 is selected, the selection circuit 6 determines which of the instruction buffer 8 and the operand buffer 9 should store the output data of the SVP4 by the SVP command control circuit 7
Is determined by the control signal from.

The output of each instruction buffer 8 and each operand buffer 9 is input to a vector instruction transmission control circuit 10. When the instruction and the operand have been stored in all the instruction buffers 8 and the operand buffers 9 respectively according to the control signal from the SVP command control circuit 7, the vector instruction transmission control circuit 10 sends the instruction buffer 8 to the SVP command control circuit 7 from the SVP4. And a command for activating the vector instruction stored in the operand buffer 9. Thus, the vector instruction is activated.

Instructions and operands are sent to each operation pipeline of the vector operation unit 12 and processed. The vector instruction management unit 11 manages the operation processing, and notifies the end of the operation to the SVP 4 via the SVP command control circuit 7.

The memory access control unit 5 controls access to the memory 2 so that the vector unit 3 functions as a processor.

 Hereinafter, the operation of the circuit shown in FIG. 1 will be described.

In the operation test of the vector unit 3, first, the SVP4 sends an SVP command to the SVP command control circuit 7 for setting the test mode. SVP command control circuit 7
Decodes the SVP command, finds out that the test mode is set, and sends a control signal to each selection circuit 6 to select the output of SVP4 from the two outputs of CPU1 and SVP4. The all-selection circuit 6 is ready to input test data from SVP4.

The instruction and the operand are sent from the SVP 4 to the selection circuit 6, and the SVP command indicating whether the instruction or the operand
It is sent to the VP command control circuit 7. The SVP command control circuit 7 decodes this SVP command, and when the input to the selection circuit 6 is an instruction and an operand,
A control signal instructing output to instruction buffer 8 and operand buffer 9 is sent out. In this way,
Instructions and operands are stored in an instruction buffer 8 and an operand buffer 9, respectively.

When the storage of the instruction and the operand in the instruction buffer 8 and the operand buffer 9 is completed, a command for starting is sent from the SVP4 to the SVP command control circuit 7, and the SVP command control circuit 7 sends the vector instruction transmission control circuit 10 to the vector instruction transmission control circuit 10. Activation of the execution of the vector instruction is instructed, and the vector operation is performed.

The vector instruction management unit 11 manages the execution state of the vector operation. When all the instructions stored in the instruction buffer have been executed, the S
Signals the completion of instruction execution to VP4.

 SVP4 sets a new instruction group.

The operation of the above vector unit 3 is independent of CPU1.
It is controlled by the operation of SVP4.

〔The invention's effect〕

According to the present invention, since the internal operation test of the vector unit can be performed independently of the operation test of the CPU, the operation test period of the entire supercomputer system can be shortened, and the test from manufacturing to product shipment can be performed. The process can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of the present invention. 1 ... CPU, 2 ... Memory, 3 ... Vector unit,
4 ... SVP, 5 ... Memory access control unit, 6 ...
... Selection circuit, 7 ... SVP command control circuit, 8 ... Instruction buffer, 9 ... Operand buffer, 10 ... Vector instruction transmission control circuit, 1 ... Vector instruction management unit, 12 ...
Vector operation unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-297736 (JP, A) JP-A-62-121742 (JP, A) JP-A-1-319854 (JP, A) (58) Survey Field (Int.Cl. ⁶ , DB name) G06F 15/177

Claims (6)

(57) [Claims] A first type of instruction is processed by itself, a second type of instruction is a first processor for transferring to another, and a second type of instruction transferred from the first processor is provided for the first type of instruction. A second processor for processing; and an external device for supplying a second type of instruction to the second processor, wherein the second processor has an output of the first processor and an output of the external device. And a buffer register for storing an output of the selection circuit. 2. A data processing apparatus according to claim 1, further comprising means for enabling a selection operation by said selection circuit means to be controlled by a command from said external device. 3. The selection circuit means has at least one selection circuit, and the buffer register means has at least one instruction and operand buffer register pair respectively connected to the output of each selection circuit. The data processing device according to claim 2, wherein 4. A means for controlling a selection operation of each of said at least one selection circuit so as to be simultaneously performed by a command from said external device, and an output of each of said selection circuits to said instruction buffer register and said operand. 4. The data processing apparatus according to claim 3, further comprising means for controlling which of the external buffer registers is to be stored from the external device. 5. The data processing apparatus according to claim 3, further comprising: means for starting processing of the instruction group stored in said buffer register means by a command from said external device. 6. A data processing apparatus according to claim 5, further comprising means for notifying said external device from said second processor that the processing of the instruction group stored in said buffer register means has been completed.