JPH05108697A - Processing system/method for vector instruction with scalar operand - Google Patents

Abstract

PURPOSE:To process a vector instruction at a high speed by carrying out the transfer of the vector data end the vector instruction with a scalar operand. CONSTITUTION:A data transfer switch instruction part 801 detects a vector instruction with a scalar operand and interrupts the transfer of the vector data if a fact that a bus is busy to transfer the vector data. Thus the part 801 produces an instruction to transfer the scalar data instead of the vector data. Then a transfer instruction is started to transfer the vector data to a vector unit 30 from a scalar unit 20 via the bus 40. Then the vector instruction with a scalar operand which includes the scalar data in an input or output operand is started after the transfer of the vector data is started. Thus the transfer of the vector data is interrupted and the scalar data is transferred instead. Then the interrupted transfer of the vector data is started again when the end of the transfer of the scalar data is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector instruction processing method and method with a scalar operand, and more particularly to vector data read from a main memory and held in a scalar unit or held in a scalar unit. Transfer scalar data to vector unit via data bus,
The present invention relates to a vector instruction processing device and method with a scalar operand for processing a vector instruction in which transferred vector data or scalar data is used as an input operand or an output operand.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 6, a main storage device 1 in which vector data is stored, a load / store unit 6 for holding read vector data, a scalar register 7 for holding scalar data, and Switching unit 65 for switching transfer of scalar data or vector data according to an instruction
And a scalar unit 62 for processing scalar data
And a data bus 4 for transferring either the scalar data or the vector data, and a calculation unit 631 for calculating the vector data or the scalar data transferred via the bus 4 for processing the vector data. And a vector unit 63 for performing. In the vector instruction processing method with the scalar unit according to the conventional example, since the arithmetic unit 631 of the vector unit 63 performs the vector operation, the vector data read from the main storage device 1 through the scalar unit 62 is transferred to the data bus 4. To transfer via. At this time, as shown in (1) of FIG. 5, in the conventional example, when the arithmetic unit 631 provided in the vector unit 63 performs vector arithmetic, the data bus 4 Vector data as operands are all vector units through
The vector operation will be performed after the data is transferred into the area 3.

[0003]

By the way, in the vector operation, there are some combinations as follows, where V is vector data and S is scalar data. That is, a. V ₁ * V ₂ = V ₃ b. V ₁ * S ₂ = V ₃ c. V ₁ * S ₂ = S ₃ d. V ₁ * V ₂ = S ₃ Here, * indicates calculation. On the other hand, many vector computers have a scalar unit and a vector unit, and perform scalar operation and instruction processing (decoding, address calculation) in a scalar unit (hereinafter referred to as S
U) 62, vector operation is performed by a vector unit (hereinafter V
U) 63, and two units are operated at the same time to increase the speed. In this case, the vector data is VU
V is stored in the vector register (hereinafter VR) in 63
Used in U63. On the other hand, scalar data is mainly SU
Since it is used by the 62, it is provided in the SU 62. Therefore,
B. Above. c. In the calculation of the type, S ₂ from SU62,
It needs to be transferred to the VU 63. Also, c. d. In the type operation, it is necessary to transfer S ₃ from VU 63 to SU 62. In order to exchange instructions and data between the VU 63 and the SU 62 in the vector computer, it is common to have independent buses. Since the data bus 4 sends wide data at one time, it has a large number of bits and the instruction bus is usually narrower than that. When sending data to a VR in a vector computer, there are a method 1 for loading data in the VU 63 and a method 2 for loading data through the SU-VU data bus 4 described above using the data fetch / store function in the SU 62. is there. Method 1 is used for high performance, and Method 2 is used for low cost. When method 2 is adopted, the SU-VU data bus 4 becomes busy during data loading / storing, and during this time, other data cannot be spliced between SU-VU. B. c. d.
The type of operation has a problem that it is kept waiting until the data bus 4 becomes free. By the way, in order to solve this problem, a new data bus is prepared. Have a copy of the scalar register in the VU. Method 1 is adopted. However, all of them have a problem that they bring about new cost increase and lose the merit of low cost of adopting the method 2. Therefore, in the present invention, the vector load / store occupies the data bus for a long time corresponding to the vector length, whereas the operation with a scalar operand only loads / stores one or two scalar data, and the data bus occupation time is long. Focusing on the shortness,
By restarting vector load / store, the purpose is to process an operation with a scalar operand without waiting.

[0004]

In order to solve the above technical problems, the first invention is, as shown in FIG. 1, a main storage device 10 in which vector data is stored and read vector data. A scalar data storage unit 60 for storing scalar data, a scalar data storage unit 70 for storing scalar data, and a switching unit 50 for switching transfer of scalar data or vector data according to an instruction, and a scalar unit 20 for processing scalar data. A data bus 40 for transferring either scalar data or vector data, and an instruction processing unit for processing a vector instruction having vector data or scalar data transferred via the bus 40 as an input operand or an output operand. A vector unit 30 having 110 and a vector instruction processing method with a scalar operand having There are instructions sent from the scalar unit 20 is, as with the scalar operand vector instruction detection unit ₈₀₂ that detects whether or not the a vector instruction with scalar operands containing either one scalar data input operands and output operands A scalar data transfer detection unit 120 for detecting whether or not the bus 40 is currently used,
Vector instruction with scalar operand detected, bus 40
When it is detected that is currently used for the transfer of vector data, the data transfer switching instructing unit 80 ₁ for interrupting the transfer of the data and for switching to the transfer of the scalar data instead is provided. Is.

On the other hand, in the second invention, as shown in FIG.
Vector data read from the main memory, or
Either one of the scalar data is transferred from the scalar unit to the vector unit via the data bus (S1),
In a vector instruction processing method with a scalar operand that processes a vector instruction that uses transferred vector data or scalar data as an input operand, a transfer instruction that transfers vector data from a scalar unit to a vector unit via a data bus is activated. After the transfer of vector data is started (S1), a vector instruction with a scalar operand containing scalar data in either an input operand or an output operand is activated (S2).
And an instruction to suspend the vector data transfer (S3),
Instead, a scalar data transfer instruction is issued (S4), and when it is detected that the scalar data transfer has been completed (S4).
5) Resuming the transfer of the interrupted vector data (S)
6) It is.

[0006]

Next, the operation of the present invention will be described. Figure 1
As shown in FIG. 2, either the vector data read from the main memory 10 and held in the scalar unit 20 or the scalar data held in the scalar data holding unit 70 of the scalar unit 20 according to the preceding instruction. One of them starts transfer to the vector unit 30 via the data bus 40 in step S1. afterwards,
In step S2, an instruction with a scalar operand is activated,
When detected by the instruction detecting unit with scalar operand 80 ₂ , the transfer of the vector data is interrupted in step S3, and the data transfer switching instruction unit 80 _{1 is} sent to the switching unit 50 of the scalar unit 20 in step S4. By this, transfer of scalar data instead of vector data is instructed. Where "instruction with scalar operand"
Is an instruction that contains scalar data in either the input operand or the output operand, and the "input operand" is the target of various instructions (for example, operation instruction) as described above (for example, operand Child)
The “output operand” is obtained as a result of instruction execution. For example, when the output operand is scalar data, there is scalar data obtained by vector inner product operation of vector data and vector data. In step S5, when the data transfer detection unit 120 detects that the transfer of the scalar data is completed,
In step S6, the interrupted transfer of vector data is restarted. In this way, the instruction processing unit 110 can process the instruction with the scalar operand by using the vector data and the scalar data.

[0007]

EXAMPLES Examples of the present invention will be described. FIG. 3 is a block diagram showing an entire apparatus according to the instruction processing method and method with a scalar operand according to the present embodiment. As shown in the figure, an apparatus for implementing the instruction processing method and method according to the present embodiment is a scalar mainly composed of a main memory 1 in which vector data is stored and a scalar CPU for processing scalar data. Unit 2, vector unit 3 for processing vector data, and scalar unit 2
And a data bus 4 for transferring either the vector data or the scalar data between the vector units 3.

The data bus 4 is included in the main memory 1.
It has a control unit 11 for sending out an interlock signal and various control signals for interrupting the data transfer. In addition, as shown in FIG.
The vector data read out from the vector unit 3 is loaded (loaded) into the vector unit 3, and the vector data transferred from the vector unit 3 is held (stored). / Store unit 6 and GR (general-purpose register G
eneral Resistor) and FR (Floating point register Floa)
ing register), which is a scalar data holding unit 70 corresponding to a scalar data holding unit 70, and an instruction read from the main storage device 1 are decoded, and instructions relating to the vector data are sequentially transmitted to the vector unit 3 or various instructions are issued. And a multiplexer 5 corresponding to a switching unit 50 for switching data transfer between the vector data held in the load / store unit 6 and the scalar data held in the scalar register 7. Corresponding to the scalar data transfer detection unit 120, outputs a bus busy signal indicating whether or not the data bus 4 is in use, and outputs an interlock signal from the control unit 11 of the main storage device 1. , The data bus 4 by the interlock signal output from the data bus control unit 8 described later.
Data control unit 22 for interrupting the data transfer of the data and for instructing the multiplexer 5 to switch the data transfer.
And an OR element 23 that synthesizes the interlock signals from the main memory device 1 and the data bus controller 8.

Further, as shown in the figure, the vector unit 3 is pipelined by a vector operation using vector data or scalar data as an input operand or an output operand (a plurality of small functional units are connected in series). And a vector register for temporarily holding the vector data transmitted via the bus 4. The arithmetic pipeline 31 performs the input of data and the output of the result at a certain time in the processing performed by the function configured by Three
2 and a control unit 9 for performing various controls of the vector unit 3
Have and. Further, as shown in the figure, the control unit 9 sequentially holds the commands sent from the command control unit 21 of the scalar unit 2 and waits in the command queue 90 for waiting for command execution and the command queue 90. An instruction register 91 for holding the next instruction to be executed in parallel,
92 and 93, and the data bus control unit 8 provided by this embodiment.

FIG. 4 shows the data bus control section 8 in detail. As shown in the figure, the data bus control unit 8 sends data from the scalar unit 2 to the instruction queue 90.
After waiting for, the activated instruction is a vector instruction detection unit 8 ₂ with a scalar operand that detects whether or not the activated instruction is a vector instruction with a scalar operand including scalar data in either an input operand or an output operand. Vector instruction with scalar operand detected, data bus 4
When it is detected that is currently used for the transfer of vector data, the transfer of the data is interrupted, and an instruction to switch to the transfer of scalar data is issued instead. At that time, from the operation pipeline 31 Data transfer switching instructing section 8 ₁ for interrupting the instruction processing from the time when the processing request signal of
Is to have. Further, as shown in the figure, the vector instruction detection unit 8 ₂ with the scalar operand has decoders 84 and 8 for decoding the instruction from the instruction queue 90.
Has 6,88, the data transferred to the switching instruction portion 8 _1, the AND element 82 and 83 for taking a logical product of the output lines of the decoder 84, 86 and the bus busy signal line or the like,
85, a scalar data transfer signal line indicating that scalar data has been transferred through the data bus 4 to the reset terminal, and a processing request signal output from the operation pipeline 31 or an output from the AND element 81. Input to the set terminal, the interlock signal for the data control unit 22 of the scalar unit 2 and the arithmetic pipeline 3
Flip-flop with set / reset that outputs an interlock signal for 1 (hereinafter referred to as "FF with SR") 8
1 and 87.

Next, the operation of the instruction processing method and method with a scalar operand according to this embodiment will be described. Figure 5
As shown in (2), the instruction control unit 21 of the scalar unit 2
When a vector load instruction, which is a preceding instruction waiting in the instruction queue 90 via the instruction bus, is activated from the main memory device 1, the vector data held in the load / store unit 6 inside the scalar unit 2 becomes Data control unit 2
2 is transferred to the vector unit 3 through the data bus 4 and held in the vector register 32 of the vector unit 3. The data bus 4 requires a processing time of vector length + α until the execution of the vector load instruction is completed.

While the vector load instruction is being activated, the subsequent instruction "V + S" (addition operation of vector data and scalar data) of the vector load instruction is activated, but the input operand S is a scalar register 7 in the scalar unit 2. Since the data is supplied to the operation pipeline 31 through the data bus 4, in the conventional case, the data bus 4 is kept waiting while busy and the processing is started after the vector loading is completed. However, in the embodiment according to the present invention, the subsequent instruction V + S is activated, and the scalar-operand-added instruction detection unit 8 ₂ of the data bus control unit 8 detects that the subsequent instruction corresponds to the scalar-operand-added instruction. When a signal indicating that fact and a busy signal indicating that the data bus 4 is in use are input to the data transfer switching unit 8 ₁ of the data bus control unit 8 shown in FIG. 4, the logical product of these signals is calculated. Then, the interlock signal is input to the set terminal of the FF with SR 81, the interlock signal is sent to the data control unit 22 of the scalar unit 2, and the vector unit 3 is supplied from the load / store unit 6.
Data transfer to the vector register 32 therein is temporarily suspended, and the multiplexer 5 is switched to transfer of vector data to scalar data.

[0013] At this time, the operation pipeline 31 sends out the processing request signal for requesting the scalar operands to execute the instruction with scalar operand data switching instruction unit _81, to the operation pipeline 31, for operation pipeline Output the interlock signal of the operation pipeline 31
Execution will be suspended. In this way, the scalar data output from the scalar register 7 is transferred via the data bus 4, whereby the scalar data is supplied to the arithmetic pipeline 31 of the vector unit 3. When the process ends, a scalar data transfer signal is input from the data control unit 22 to the data transfer switching instructing unit 8 ₁ via the control bus, and the FF 81 enters the reset state,
The interlock signal is released. When the interlock signal is released, the transfer of vector data interrupted by the data control unit 22 is restarted. As a result, vector loading and V + S operation instructions can be executed in parallel.
In FIG. 5 (2), the b. Type (when the input operand is vector data and scalar data and the output operand is vector data), the same c. Type (when input operand is vector data and scalar data and output operand is scalar data), same figure
In (2), d. The type (when the input operand is vector data and the output operand is scalar data) is shown.

[0014]

As described above, according to the present invention, as soon as the instruction with the scalar operand is activated, the data transfer via the data bus by the load instruction of the vector data is temporarily interrupted, and the scalar data is transferred in the meantime. Is performed, and the interrupted vector data transfer is restarted as soon as the transfer of the scalar data is completed. Therefore, the transfer of vector data and the instruction with the scalar operand can be executed in parallel, and the processing speed of the instruction can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the first invention.

FIG. 2 is a principle flowchart according to the second invention.

FIG. 3 is an overall block diagram according to an embodiment.

FIG. 4 is a block diagram showing a data bus control unit according to the embodiment.

FIG. 5 is a time chart according to an example and a conventional example.

FIG. 6 is a block diagram according to a conventional example.

[Explanation of symbols]

10, 1 Main memory 20, 2 Scalar unit 30, 3 Vector unit 40, 4 Data bus 50, 5 Switching unit (multiplexer) 60 (6) Vector data holding unit (load / store unit) 70 (7) Scalar data holding Section (scalar register) 80 ₁ , 8 ₁ data transfer switching section 80 ₂ , 8 ₂ vector instruction detecting section with scalar operand 110 (31) instruction processing section (arithmetic pipeline) 120 (22) scalar data transfer detecting section (data control Part)

Claims (4)

[Claims] 1. A main storage device (10) in which vector data is stored, a vector data holding unit (60) holding the read vector data, a scalar data holding unit (70) holding scalar data, and an instruction. Has a switching unit (50) for switching transfer of scalar data or vector data by means of a scalar unit (20) for processing scalar data, and a data bus for transferring either scalar data or vector data ( 40) and a vector unit (30) having an instruction processing unit (110) for processing a vector instruction having vector data or scalar data transferred via the bus (40) as an input operand or an output operand. In the vector instruction processing method with a scalar operand, the scalar unit (20) sends Instructions, input operands or with a scalar operand vector instruction detection unit that detects whether or not the a vector instruction with scalar operands containing scalar data to either the output Openrado and (80 _2), the bus (40) is currently A scalar data transfer detection unit (120) for detecting whether or not it is in use, and a vector instruction with a scalar operand are detected, and a bus (4
If it is detected that 0) is currently used for vector data transfer, the data transfer switching instructing section (80 ₁ ) for interrupting the data transfer and instructing to switch to the scalar data transfer instead. A vector instruction processing method with a scalar operand characterized by being provided. 2. The data transfer switching instruction unit (80 ₁ )
If a vector instruction with a scalar operand is detected and it is detected that the bus (40) is currently used for the transfer of vector data, the transfer of that data is interrupted, and instead the transfer of scalar data is performed. At the same time as issuing an instruction to switch, it is possible to interrupt the instruction processing from the time when there is a processing request signal from the instruction processing unit (110) that performs instruction processing such as calculation until the transmission of scalar data ends. The vector instruction processing system with a scalar operand according to claim 1, characterized in that. 3. The vector instruction processing method with a scalar operand according to claim 1, wherein the instruction processing unit is an arithmetic pipeline. 4. Either the vector data read from the main memory or the scalar data is transferred from the scalar unit to the vector unit via the data bus (S1), and the transferred vector data or the scalar data is transferred. In the vector instruction processing method with a scalar operand that processes a vector instruction that uses data as an input operand, a transfer instruction that transfers vector data from the scalar unit to the inside of the vector unit via the data bus is activated, and the transfer of vector data starts. After that (S1), when a vector instruction with a scalar operand that contains scalar data in either the input operand or the output operand is activated (S2), the interruption of the vector data transfer is instructed (S3). Instruct to transfer scalar data (S4) When the transfer of data is completed is detected (S
5) A vector instruction processing method with a scalar operand, characterized in that the transfer of the interrupted vector data is restarted (S6).