JPH0685166B2 - Instruction control method for multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a multiprocessor system in which a plurality of processors (first processors) request one processor (second processor) to execute a specific process, the second processor is the first processor. The usage right given to the first processor is automatically changed by identifying the instruction group in the instruction sequence from. Each of the first processors does not need to be aware of the race condition between them, and the efficient processing is performed.

[Industrial application field]

The present invention relates to an instruction control method for instruction processing between processors in a multiprocessor system, and more particularly to an instruction control method useful in a computer system having a configuration in which a plurality of scalar units share one vector unit.

[Conventional technology]

Scientific and technological computers are generally composed of a scalar unit that processes scalar instructions (hereinafter referred to as SU) and a vector unit that processes vector instructions (hereinafter referred to as VU).

The VU can process the same multiple operations at high speed. Therefore, in a computer, the higher the VU usage rate, the higher the performance. But in the program,
Some are difficult to vectorize, that is, some are difficult to convert into vector instructions. In such a program, V
Usage rate of U becomes low.

Therefore, a multiprocessor system in which multiple SUs are connected to one VU has been proposed.

FIG. 3 is an example of such a multiprocessor system, and shows a system configuration including two SUs and one VU.

In the figure, 30 is a main memory unit (represented by MSU), 31 is a storage control unit (represented by MCU), 32 is a vector processing unit (represented by VPU), and 33 and 34 are scalar units (SU ₀ , SU ₁ respectively). , 35 is a vector unit (represented by VU).

SU ₀ and SU ₁ are each coupled to MSU via MCU,
Independently execute program processing in parallel. SU ₀ and SU ₁
Requests the VU to process when the instruction to be executed is a vector instruction. The VU executes the requested vector instruction and returns the result to the requesting SU via the MSU.

Fig. 4 shows the internal structure of the VU in Fig. 3, where 40 is MSU, 41 is MCU, 42 is VPU, 43 is SU ₀ , 44 is SU ₁ and 45 is VU.
And correspond to 30 to 35 in FIG. 3, respectively.

In the VU, 450 is a vector control unit (represented by VCU), 451 is a vector execution unit (represented by VEU), 452 is a control signal, 453 is a load pipeline, 454 is a store pipeline, and 455 is a vector register (VR. , 456 is ADD
Pipeline (denoted by ADD), 457 is the multiplication pipeline (M
ULTI), 458 represents the DEVIDE pipeline.

The VCU 450 is a unit that controls vector instructions, and the control signal 452 controls instruction execution in the VEU 451.

The VEU451 is a unit that executes vector instructions.
It has a load pipeline 453 that transfers vector data to and from 40, a store pipeline 454, and a VR455 that holds vector data. Furthermore, instructions that read the vector data from the VR455, perform an operation, and write the result to the VR455 AD for addition, multiplication, and division, respectively, to execute
It has a D pipeline 456, a MULTI pipeline 457, and a division pipeline 458.

SU ₀ and SU ₁ fetch the instruction from MSU through MCU respectively. If the instruction is a scalar instruction, it is processed in its own unit, and if it is a vector instruction, it is sent to the VCU.

From the perspective of the VCU, the VEU is the only unit that can execute vector instructions, but the request sources that send vector instructions are SU ₀ and SU ₁ . Therefore, when the vector instructions from SU ₀ and SU ₁ conflict, it is necessary to select one to process.

[Problems to be solved by the invention]

In a conventional multiprocessor system, when a plurality of processors request processing to one specific processor, it is necessary to perform contention control between the plurality of requesting processors, and the processing overhead is reduced due to the overhead. was there.

[Means for solving problems]

The present invention eliminates the need for contention control among a plurality of processors (referred to as a first processor) described above, and enables a specific processor (referred to as a second processor) to switch the usage right easily and quickly.

Therefore, according to the configuration of the present invention, in the instruction control system of the multiprocessor system in which the instructions from the plurality of first processors are processed by the single second processor, the first processor which is currently given the usage right in the second processor sends the instruction. An instruction buffer for storing an arbitrary number of instructions is provided, and when storing the instruction in the instruction buffer, information indicating which of the first processors is the request source is added. By using the information to detect a state in which all the instructions of one of the first processors to which the usage right has been given have not been executed, the second processor causes the plurality of first processors to operate.
It is characterized in that the right of use of the second processor is changed among a plurality of first processors for every arbitrary number of instructions from each of the processors and a new instruction is accepted.

FIG. 1 (a) is a diagram showing the principle configuration of the present invention.
In the figure, 10 is a scalar unit SU ₀ , 11 is a scalar unit SU ₁ , 12 is a vector unit VU, 101 and 111 are buses, and 12
0 and 121 are instruction fetch registers, 122 is selector, 123
Is a command transmission buffer, 124 is an SU display flag, 125 is a command group identification circuit, and 126 is a usage right setting circuit.

Here, the scalar units SU ₀ and SU ₁ correspond to the above-mentioned first processor, and the vector unit VU corresponds to the above-mentioned second processor.

The scalar unit SU ₀ or SU ₁ sends an instruction to the vector unit VU via the buses 101 and 111, respectively, when it is necessary to execute the vector instruction.

In the vector unit VU, the instructions sent from the scalar units SU ₀ , SU ₁ are fetched by the instruction fetch registers 120, 12 respectively.
The data is temporarily stored in 1, and one is selected by the selector 122, that is, the instruction fetch register on the side of the scalar unit to which the right to use the VU is given is selected and transferred to the instruction transmission buffer 123.

The command transmission buffer 123 is composed of a stack of multiple stages, and S
Instruction sequences input from U ₀ or SU ₁ are stored sequentially. The instructions stored in this buffer are read in the order of input and executed by the vector execution unit VEC.

An SU display flag 124 is provided at each stage of the command transmission buffer 123, and each time the command is stored, it is determined whether the requester (issuer) scalar unit of the command is SU ₀ or SU _1. The indicated value is set. The value of the SU display flag 124 is set by the usage right setting circuit 126.

The instruction group identification circuit 125 checks the SU display flag 124 of the instruction transmission buffer 123 to find that the instruction of the scalar unit to which the right of use is currently given has disappeared from the buffer, that is, the instruction stored in the buffer for that scalar unit. Is detected and it is detected that no new instruction is supplied, it is determined that the instruction sequence is a break and an instruction group delimiter signal is sent to the usage right setting circuit 126.

When the instruction group break signal is sent from the instruction group identification circuit 125, the usage right setting circuit 126 changes the currently granted scalar unit to the other scalar unit and switches the selector 122 accordingly. Then, when the instruction sequence input via the instruction fetch register on the side of the scalar unit to which the new usage right is given is stored in the instruction transmission buffer 123, the SU display flag 124 corresponds to the scalar unit to which the new usage right is given. Set the value to

The above operation can be repeated arbitrarily.

[Action]

The operation based on the configuration of the present invention described with reference to FIG.
A specific description will be given with reference to the instruction execution sequence example shown in FIG.

The figure shows the instruction sequence and VU executed in SU ₀ and SU ₁ , respectively.
It shows the transfer control of the right to use. The symbol V,
V ′ is the vector instruction of SU ₀ and SU ₁ , respectively, and S and S ′ are respectively
It represents a scalar instruction for SU ₀ and SU ₁ .

First, assuming that the right to use VU is given to SU ₀ , S
Together with TART, SU ₀ sends vector instructions V ₁ to V ₃ to VU for execution. Since the instruction sequence is interrupted in VU while SU ₀ is executing the subsequent scalar instructions S ₁ and S ₂ , VU determines that one instruction group is completed and transfers the usage right to SU ₁ . As a result, SU ₁ sends vector instructions V ₁ ′ to V ₄ ′ to VU for execution, and subsequent scalar instructions S ₁ ′ and S ₂ ′ are executed by SU ₁ . Therefore, the VU determines that the instruction sequence has been interrupted and the VU has finished the next instruction group, and the VU transfers the usage right to SU ₀ .

In the same manner, V ₄ to V _{6 of} SU ₀ are further changed in usage right, and V ₅ ′ to V ₇ ′ of SU ₁ are executed by VU, respectively.

If the principle of the present invention is applied to an arbitrary plurality of scalar units, the vector unit is made to identify the instruction group by the method described above for each instruction sequence, and the instruction group unit is allowed to switch the usage right for each scalar unit. You can

[Embodiment] FIG. 2 is a configuration diagram of a system according to an embodiment of the present invention.

In the figure, 20 is SU ₀ , 21 is SU ₁ and 22 is VU, which corresponds to the elements 10 to 12 in FIG. 1 (a). In addition, 201 and 211 are busses for transferring instructions, 202 and 212 are signal lines for instruction fetch prohibition signals, 220 and 230 are instruction fetch registers VFSR ₀ , VFSR ₁ , 221, and 231 are instruction fetch buffers VFB ₀ , VFB ₁ , 222, and 232 are instruction fetch registers and instructions. Selector SEL, 223, 233 for switching the buffer register is an AND circuit for selecting the instruction of the scalar unit to which the usage right is given, 224, 234 is a latch for setting the usage right, 225, 235 is an AND circuit for switching the setting status of the usage right, 226, 236 is a group of instructions. A NOR circuit for identifying a break, 227 and 237 are inversion circuits that generate an instruction fetch prohibition signal, 228 is an instruction output buffer, and 228a and 228b are SU ₀ and SU _{1 which} are request sources of vector instructions, respectively.
SU display flag for displaying and, 229 for bus, respectively.

Next, the operation will be described. For example, assume that a vector instruction is sent from SU ₀ to the instruction fetch register VFSR ₀ 220 via the bus 201. At this time, the instruction fetch buffer VFB ₀ 22
If 1 is empty and the latch 224 indicating the VU usage right of SU ₀ is in the set state, the command is transmitted and stored in the command transmission buffer 228 through the selector SEL222 and AND circuit 223, and the SU display flag 228a is also stored. Is set to "1".

The instruction stored in the instruction transmission buffer 228 is then read out, transmitted from the instruction transmission buffer 228 through the bus 229 to the vector execution unit VEU (not shown) and executed. The latches 224 and 234 are in an antithetical relationship, and when the latch 224 is “1”, the latch 234 is “0”. That is, when SU ₀ is given the right to use VU, SU ₁
I do not have the right to use U. Further, at this time, the inverting circuit 237
Through, a signal line 212 sends an instruction fetch prohibition signal to SU ₁ .

Upon receiving this instruction fetch prohibition signal, SU ₁ stops sending instructions to VU. Note that the instruction sent before this instruction fetch prohibition control is executed is the instruction fetch register VFSR.
_It is sent from the ₁ 230 to the instruction fetch buffer VFB ₁ 231, and stored there.

Here, when the command transmission from SU ₀ is interrupted and the command transmission from the command transmission buffer 228 progresses and the buffer becomes empty, the SU display flags 228a at each stage, which are inputs to the NOR circuit 226, are all set to "0". Then, the NOR circuit 226 outputs an instruction group division signal (= "1") indicating the end of one instruction group. As a result, the output of the AND circuit 235 becomes "1", the latch 225 is reset, and the latch 235 is set. That is, the right to use VU is transferred from SU ₀ to SU ₁ .

As a result, the vector instruction that was previously stored in the instruction fetch buffer VFB ₁ 231 will be stored in the selector SEL232 and AND circuit 23.
3 is transmitted to the command transmission buffer 228. This command is stored in the command transmission buffer 228, and at the same time, its SU display flag 228b is set to "1".

The command from SU ₁ stored in command transmission buffer 228 is then transmitted to VEU via bus 229. And NOR circuit 2
36 functions similarly to the NOR circuit 226 described above, and when the delimiter of the instruction group is identified, the states of the latches 224 and 234 are inverted,
Change the usage rights setting. This operation is repeated as many times as necessary.

〔The invention's effect〕

According to the present invention, the second processor automatically identifies the delimiter of the instruction group and switches the usage right given to each first processor, so that the contention control between the first processors can be efficiently performed.

That is, for example, when there is no vector instruction for a while after a succession of vector instructions, it is possible to easily give the usage right to another SU by the judgment of only the vector unit.

[Brief description of drawings]

1 (a) is a block diagram showing the principle of the present invention, FIG. 1 (b) is an instruction execution sequence diagram for explaining the operation of the present invention, and FIG. 2 is a block diagram of a system of one embodiment of the present invention. FIG. 3 is a block diagram of an example of the multiprocessor system, and FIG. 4 is an internal block diagram of the VU. In FIG. 1 (a), 10: scalar unit SU ₀ 11: scalar unit SU ₁ 12: vector unit VU 120, 121: instruction fetch register 122: selector 123: instruction output buffer 124: SU display flag 125: instruction group identification circuit 126 : Usage right setting circuit

Claims (1)

[Claims] 1. An instruction control method for a multiprocessor system in which instructions from a plurality of first processors (10, 11) are processed by a single second processor (12), and is currently used in a second processor (12). The first empowering
An instruction buffer for storing an arbitrary number of instructions sent from the processor is provided, and when storing the instruction in the instruction buffer, information indicating which of the first processors is the request source is added, and this buffer is added. From the above, the second processor (12) detects a state in which all the instructions of one of the first processors to which the right of use is currently given have not been executed, and the second processor (12) has a plurality of instructions. 1 processor (10,1
An instruction control method for a multiprocessor system, characterized in that the right to use the second processor (12) is changed among a plurality of first processors for each arbitrary number of instructions from (1) and a new instruction is accepted. .