JPS5461851A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5461851A
JPS5461851A JP12897777A JP12897777A JPS5461851A JP S5461851 A JPS5461851 A JP S5461851A JP 12897777 A JP12897777 A JP 12897777A JP 12897777 A JP12897777 A JP 12897777A JP S5461851 A JPS5461851 A JP S5461851A
Authority
JP
Japan
Prior art keywords
regions
processors
cpub
cpua
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12897777A
Other languages
Japanese (ja)
Inventor
Toshio Awaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12897777A priority Critical patent/JPS5461851A/en
Publication of JPS5461851A publication Critical patent/JPS5461851A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To control easily a multi-processor system which processes a plural number of instructions simultaneously by being provided with a plural number of data processors, by simplifying each processor by executing an option instruction by a common-use arithmetic unit in common with each processor.
CONSTITUTION: This system is provided with data processors CPUA and CPUB, memory units M1 and M2 accessed from those processors CPUA and CPUB, and common-use arithmetic unit CALU accessing to units M1 and M2. Further, units M1 and M2 are provided with specific regions AA and AB assigned being classified by processors CPUA and CPUB, which execute instructions stored in regions AA and AB respectively. At the time of reading out instructions to be processed by unit CALU, processors CPUA and CPUB store instruction information, operation data, and operand data information in their own regions AA and AB before sending an actuation signal to unit CALU, read out each information from regions AA and AB for calculation, and then, store arithmetic results in regions AA and AB.
COPYRIGHT: (C)1979,JPO&Japio
JP12897777A 1977-10-27 1977-10-27 Data processing system Pending JPS5461851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12897777A JPS5461851A (en) 1977-10-27 1977-10-27 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12897777A JPS5461851A (en) 1977-10-27 1977-10-27 Data processing system

Publications (1)

Publication Number Publication Date
JPS5461851A true JPS5461851A (en) 1979-05-18

Family

ID=14998071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12897777A Pending JPS5461851A (en) 1977-10-27 1977-10-27 Data processing system

Country Status (1)

Country Link
JP (1) JPS5461851A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916072A (en) * 1982-04-21 1984-01-27 デイジタル・イクイプメント・コ−ポレ−シヨン Special instruction processor for data processing system
JPS59106075A (en) * 1982-12-10 1984-06-19 Hitachi Ltd Data processing system
JPS60129835A (en) * 1983-12-16 1985-07-11 Fujitsu Ltd Instruction controlling system
JPS6220064A (en) * 1985-07-19 1987-01-28 Fujitsu Ltd Instruction control system for multi-processor system
JPS6347835A (en) * 1986-08-18 1988-02-29 Agency Of Ind Science & Technol Pipeline computer
JPS63291155A (en) * 1987-05-22 1988-11-29 Matsushita Electric Ind Co Ltd Communication method between processors
JP2006252440A (en) * 2005-03-14 2006-09-21 Fujitsu Ltd Reconfigurable arithmetic processing unit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916072A (en) * 1982-04-21 1984-01-27 デイジタル・イクイプメント・コ−ポレ−シヨン Special instruction processor for data processing system
JPS6252345B2 (en) * 1982-04-21 1987-11-05 Digital Equipment Corp
JPS59106075A (en) * 1982-12-10 1984-06-19 Hitachi Ltd Data processing system
JPH0461390B2 (en) * 1982-12-10 1992-09-30 Hitachi Ltd
JPS60129835A (en) * 1983-12-16 1985-07-11 Fujitsu Ltd Instruction controlling system
JPS6220064A (en) * 1985-07-19 1987-01-28 Fujitsu Ltd Instruction control system for multi-processor system
JPS6347835A (en) * 1986-08-18 1988-02-29 Agency Of Ind Science & Technol Pipeline computer
JPS63291155A (en) * 1987-05-22 1988-11-29 Matsushita Electric Ind Co Ltd Communication method between processors
JP2006252440A (en) * 2005-03-14 2006-09-21 Fujitsu Ltd Reconfigurable arithmetic processing unit
US7743236B2 (en) 2005-03-14 2010-06-22 Fujitsu Limited Reconfigurable processor

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