JPS5475964A - Data pre-fetch system - Google Patents
Data pre-fetch systemInfo
- Publication number
- JPS5475964A JPS5475964A JP14263177A JP14263177A JPS5475964A JP S5475964 A JPS5475964 A JP S5475964A JP 14263177 A JP14263177 A JP 14263177A JP 14263177 A JP14263177 A JP 14263177A JP S5475964 A JPS5475964 A JP S5475964A
- Authority
- JP
- Japan
- Prior art keywords
- control part
- memory
- data
- cycle
- operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To obtain an information processing unit to execute effectively the processing of a long operand by providing a pre-fetch means which stores operand data from a main memory to a cache memory by block transfer.
CONSTITUTION: In the I cycle, instruction words are sent to instruction control part 13, and processings such as instruction decoding, operand address calculation, generation of a memory command for fetch request, conversion of a page address to an actual address are performed to transfer the request signal to memory access control part 14. In the C cycle, the data transfer request is accepted in control part 14 to access cache memory 11 or main memory 10 as required. Memory 11 holds data which is corresponded with main memory 10 in block. As required, accessed data is transferred to arithmetic control part 12. In the E cycle, the execution of arithmetic operation and the store of the result are performed in control part 12 on a basis of data transferred from control part 14.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52142631A JPS601655B2 (en) | 1977-11-30 | 1977-11-30 | Data prefetch method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52142631A JPS601655B2 (en) | 1977-11-30 | 1977-11-30 | Data prefetch method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5475964A true JPS5475964A (en) | 1979-06-18 |
JPS601655B2 JPS601655B2 (en) | 1985-01-16 |
Family
ID=15319824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52142631A Expired JPS601655B2 (en) | 1977-11-30 | 1977-11-30 | Data prefetch method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS601655B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5786180A (en) * | 1980-11-17 | 1982-05-29 | Hitachi Ltd | Memory device having address converting mechanism |
JPS62102344A (en) * | 1985-10-29 | 1987-05-12 | Fujitsu Ltd | Buffer memory control system |
JPS63110946U (en) * | 1987-12-10 | 1988-07-16 | ||
US6912650B2 (en) | 2000-03-21 | 2005-06-28 | Fujitsu Limited | Pre-prefetching target of following branch instruction based on past history |
JP2011034239A (en) * | 2009-07-30 | 2011-02-17 | Nec Corp | Information processor, delay determination method for load instruction, and delay determination program for load instruction |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6243060U (en) * | 1985-09-03 | 1987-03-14 |
-
1977
- 1977-11-30 JP JP52142631A patent/JPS601655B2/en not_active Expired
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5786180A (en) * | 1980-11-17 | 1982-05-29 | Hitachi Ltd | Memory device having address converting mechanism |
JPH0118457B2 (en) * | 1980-11-17 | 1989-04-05 | Hitachi Seisakusho Kk | |
JPS62102344A (en) * | 1985-10-29 | 1987-05-12 | Fujitsu Ltd | Buffer memory control system |
JPH0410102B2 (en) * | 1985-10-29 | 1992-02-24 | ||
JPS63110946U (en) * | 1987-12-10 | 1988-07-16 | ||
US6912650B2 (en) | 2000-03-21 | 2005-06-28 | Fujitsu Limited | Pre-prefetching target of following branch instruction based on past history |
JP2011034239A (en) * | 2009-07-30 | 2011-02-17 | Nec Corp | Information processor, delay determination method for load instruction, and delay determination program for load instruction |
Also Published As
Publication number | Publication date |
---|---|
JPS601655B2 (en) | 1985-01-16 |
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