JP2011034239A - Information processor, delay determination method for load instruction, and delay determination program for load instruction - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To give an index for correcting the inserting position of a prefetch instruction to a user who creates a program. <P>SOLUTION: This information processor 10 including an arithmetic unit 11 and a main storage device 13 and a cache device 12 is configured to detect a load instruction 107 to a cache device whose delay is generated during cache fill execution due to a prefetch instruction 105 from the arithmetic unit 11, and to acquire the generation frequency or duration of the detected load instruction 107. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that gives an index for correcting a prefetch instruction insertion position to a user who creates a program, a load instruction delay determination method, and a load instruction delay determination program.

  In recent technologies, the improvement rate of the memory bandwidth is smaller than the performance improvement rate of the central processing unit. Therefore, effective use of the memory bandwidth is very important for improving the performance of the computer system.

  On the other hand, the prefetch instruction is an instruction that is executed prior to the load instruction to improve the cache hit rate of the load instruction, thereby improving the performance of the program (job).

Therefore, executing a prefetch instruction at an appropriate timing enables effective use of the memory bandwidth in a time interval in which the load instruction does not use the memory bandwidth. Therefore, in recent computer systems, the prefetch instruction is executed at an appropriate timing. Execution is an important issue for improving performance.
Future research, development, and papers have proposed a hardware mechanism and a language translation device (compiler) that control this timing automatically.

  In related technologies so far, there have been proposed a plurality of technologies relating to a compiler and a hardware mechanism for controlling execution position determination of a prefetch instruction to be appropriate automatically.

  For example, in the technique disclosed in Patent Document 1, the hardware predicts the optimum execution position of a prefetch instruction from the past memory access history, and dynamically embeds the prefetch instruction in the instruction sequence during program execution. It is possible.

  However, in the technique disclosed in Patent Document 1, information on whether or not the execution position of the prefetch instruction is appropriate is not provided to the user, so the user determines whether or not the execution position of the prefetch instruction is appropriate from the job execution result. However, the insertion position of the prefetch instruction cannot be corrected appropriately.

  Note that the state where the prefetch instruction does not work effectively is the following two states.

  First, the first state is a case where prefetched data is evicted out of the cache before execution of the load instruction because the prefetch instruction is executed at a position too early with respect to the load instruction. This state can be measured with a conventional cache miss counter.

  The second state is a case where the cache fill by the prefetch instruction is not completed before the load instruction is executed because the prefetch instruction is executed at a position too late with respect to the load instruction. This state is either included in the cache miss counter in the first state, counted in the related art so far, or not observed at all. 10 and 11 show this state.

  FIG. 10 shows a case where the load instruction is held until the data is prefetched, and FIG. 11 shows a case where the data is acquired from the main memory without waiting for the data to be prefetched. .

  FIG. 9 shows a good example of the prefetch instruction execution position. In FIG. 9, since the load instruction reaches the cache after the data is prefetched into the cache by the prefetch instruction, the load instruction can acquire the data from the cache.

  A plurality of techniques for counters that count cache misses are disclosed, and further, a counter that measures the cache misses is disclosed in Patent Document 2.

  In the technique disclosed in Patent Document 2, when the counter requests all the requested data in the non-region above the prefetch area at the time of the load instruction after prefetch, or the counter extends over the non-area and cache area above the prefetch area. If they exist in the non-prefetch area below the prefetch area, or if they exist across the non-area and cache area below the prefetch area, and if they exist in the prefetch area It is possible to measure.

JP 2004-0383345 A JP2008-061151

  The problem of the related art described above is that the second state described above, that is, the case where a delay occurs in the load instruction during execution of the cache fill based on the preceding prefetch instruction, is counted as a cache miss, or Because it is ignored, it is difficult to accurately measure the delay of the load instruction due to the prefetch instruction separately from the case of a normal cache miss.

(Object of invention)
The object of the present invention is to solve the problem that the load instruction is delayed due to the execution of the cache fill based on the prefetch instruction, which is the above-mentioned problem. The present invention relates to an information processing apparatus that provides an index for correcting an insertion position, a load instruction delay determination method, and a load instruction delay determination program.

  A first information processing apparatus according to the present invention is an information processing apparatus including an arithmetic device, a main storage device, and a cache device, and a load instruction for a cache device in which a delay occurs due to execution of a cache fill by a prefetch instruction from the arithmetic device And detecting the number of occurrences or duration of the detected load instruction.

  A first load instruction delay determination method according to the present invention is a load instruction delay determination method in an information processing apparatus including an arithmetic unit, a main storage unit, and a cache unit, and a cache fill is being executed by a prefetch instruction from the arithmetic unit. And a step of detecting a load instruction for the cache device in which the delay has occurred, and a step of acquiring the number of occurrences or the duration of the detected load instruction.

  A first load instruction delay determination program according to the present invention is a load instruction delay determination program executed by an information processing apparatus including an arithmetic device, a main storage device, and a cache device, and includes a cache based on a prefetch instruction from the arithmetic device. The information processing apparatus is caused to execute a function of detecting a load instruction for a cache device in which a delay occurs during execution of fill and a function of acquiring the number of occurrences or duration of the detected load instruction.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus which gives the parameter | index for correcting the insertion position of a prefetch instruction to the user who creates a program, the delay determination method of a load instruction, and the delay determination program of a load instruction can be provided.

  This is because the number of delays and the delay time of the load instruction due to the execution of the cache fill based on the preceding prefetch instruction are measured.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a figure which shows the structure of the cache apparatus in the 1st Embodiment of this invention. It is a figure which shows the structure of the arithmetic unit in the 1st Embodiment of this invention. It is the flowchart which showed the operation | movement of the cache search in the 1st Embodiment of this invention. It is the flowchart which showed the operation | movement at the time of the prefetch instruction | command issue in the 1st Embodiment of this invention. It is the flowchart which showed the operation | movement at the time of the load instruction issuance in the cache fill in the 1st Embodiment of this invention. It is the flowchart which showed operation | movement of the arithmetic unit at the time of the detection signal reception in the 1st Embodiment of this invention. It is a block diagram which shows the hardware structural example of the computer system of this invention. It is a figure which shows the example of the prefetch execution position by related technology. It is a figure which shows the example of the execution position of the prefetch instruction | indication and load instruction | indication by related technology. It is a figure which shows the example of the execution position of the prefetch instruction | indication and load instruction | indication by related technology.

  Next, an embodiment of the present invention will be described in detail with reference to FIGS.

(First embodiment)
FIG. 1 is a diagram showing the configuration of the first exemplary embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of the cache device 12. FIG. 3 is a diagram illustrating the configuration of the arithmetic device 11.

  Referring to FIG. 1, the present embodiment includes a program code 20, a compiler 30, and an information processing apparatus 10.

  The program code 20 is a program code written by the user of the information processing apparatus 10. It is assumed that the program code 20 includes a prefetch instruction insertion instruction line (prefetch instruction instruction line).

  The compiler 30 has a function of translating and outputting the program code 20 into an instruction code 301 in a format executed by the information processing apparatus 10.

  The compiler 30 also has a function of interpreting the instruction line of the prefetch instruction. The compiler 30 is assumed to be, for example, a C / C ++ / Fortran compiler. The instruction line includes a parameter for designating the execution position of the prefetch instruction.

  The language translator inserts a prefetch instruction into the instruction string of the instruction code 301 in accordance with the prefetch instruction instruction line in the program code 20.

  The instruction code 301 translated and output by the compiler 30 is stored in the main storage device 13.

The information processing apparatus 10 includes an arithmetic device 11 that performs information processing and control, a cache device 12 that temporarily holds data, and a main storage device 13 that stores data.

  The arithmetic unit 11 sends an instruction fit 100, a prefetch instruction 105, and a load instruction 107 to the cache unit 12, and receives an instruction code 103, a detection signal 110, and load data 112 from the cache unit 12.

  The cache device 12 exchanges instructions and data with the arithmetic unit 11 as described above, sends an instruction fetch 101, a prefetch instruction 106, and a load instruction 108 to the main storage device. Prefetch data 109 and load data 111 are received.

  Note that the instruction fetches 100 and 101, the instruction codes 103 and 104, the prefetch instructions 105 and 106, the load instructions 107 and 108, and the load data 111 and 112 are the same, and are separated from each other for convenience.

  The instruction fitch 100 is an instruction that requests the instruction code 103.

  The instruction codes 103 and 104 are the same as those output by the compiler 30 and stored in the main storage device 13.

  The prefetch instructions 105 and 106 are instructions for requesting prefetching of data and include an address of data to be prefetched.

  The load instructions 107 and 108 are instructions for requesting data loading, and include addresses of data to be loaded.

  The prefetch data 109 is data sent from the main storage device 13 in response to the prefetch instruction 106.

  The load data 111 is data transmitted from the main storage device 13 in response to the load instruction 108.

  The detection signal 110 is a signal that triggers counting of a counter 1010, which will be described later, and measurement start and end of a timer 1014.

  Next, referring to FIG. 2, first, the prefetch instruction 105 and the load instruction 107 have an instruction address part 1003, and prefetch or load is performed across the tag 1000, the index 1001, and the offset 1002 of the instruction address part 1003. Stores the address of the data to be performed.

  The cache device 12 manages temporarily stored data in a certain unit, and this is called a cache entry 113.

  The cache entry 113 includes a valid flag 1004, a cache fill flag 1005, a cache tag part 1007, and a cache data part 1008.

  The valid flag 1004 is a flag indicating whether or not prefetch is being executed. The value is 0 during prefetch execution, and the value is 1 when prefetch is not being executed.

The cache fill flag 1005 is a flag indicating whether or not the cache fill is being executed. The value is 1 while the cache fill is being executed, and the value is 0 when the cache fill is not being executed. Note that “cache fill” means reading data in the main storage device 13 into the cache device 12.

  The cache tag part stores the address of the cache entry 113.

  The cache data unit 1008 stores the cache-filled data in the cache entry 113.

In addition, the cache device 12 includes a detection signal generation unit 1006 that detects a condition in which the subsequent load instruction 107 refers to the cache entry 113 that is being cache-filled by the prefetch instruction 105.

  The detection signal generation unit 1006 has an AND circuit function, and inputs a logical negation of a flag value of a valid flag 1004 (to be described later), a flag value of a cache fill flag 1005, and a logical value of a cache hit or a cache miss. Note that a cache hit has a logical value 1 and a cache miss has a logical value 0.

  The detection signal generation unit 1006 detects the logical value of the flag value of the valid flag 1004, the flag value of the cache fill flag 1005, the logical value in the case of a cache hit, and the detection signal 110 of value 1 when all the input values are 1. Otherwise, a detection signal 110 with a value of 0 is output.

  Next, referring to FIG. 3, the arithmetic unit 11 includes a differentiating circuit 1011, a selector 1012, a differentiating circuit valid mode 1013, a counter 1010, and a timer 1014.

  The differentiation circuit 1011 is a circuit designed so that the output signal is a derivative of the input signal.

  The differentiation circuit 1011 receives the detection signal 110 from the cache device 12 and outputs a differentiation circuit output signal 114 that is a differential signal of the input detection signal 110.

  Note that the differentiating circuit 1011 may be provided between the detection signal generation unit 1006 in the cache device 12 and the arithmetic device 11.

That is, in the present embodiment, the differentiating circuit 1011 is provided in the arithmetic device 11, but is not limited to this, and is provided in the cache device 12 or between the cache device 11 and the arithmetic device. It is also possible to provide a separate device for the device.

  In addition, the detection signal generation unit 1006 does not use the differentiation circuit 1011 to generate a pulse signal equivalent to the differentiation circuit output signal 114, and the timer 1014 measures only the time without using the differentiation circuit 1011 and the counter 1010. Implementation is also possible. That is, this embodiment does not limit the mounting form of the present invention.

  The differentiation circuit effective mode 1013 is a mode for determining a signal output from the selector 1012.

  The selector 1012 is a circuit that outputs only one of a plurality of input signals.

  The selector 1012 receives the detection signal 110 from the cache device 12 and the differentiation circuit output signal 114 from the differentiation circuit 1011.

  The selector 1012 outputs either the detection signal 110 or the differentiation circuit output signal 114 to the counter 1010 or the timer 1014 according to the differentiation circuit valid mode 1013.

  The differentiation circuit effective mode 1013 can be arbitrarily set depending on what is desired to be measured. In the present embodiment, when it is desired to count the number of times the detection signal has changed from 0 to 1, the mode of the differentiation circuit effective mode 1013 is set to mode 1. The number of times the detection signal 110 has changed from 0 to 1 refers to the number of times the subsequent load instruction 107 refers to the cache entry 113 in the cache fill by the prefetch instruction 105.

  Further, when it is desired to measure the time during which the detection signal 110 is 1, the mode of the differentiation circuit effective mode 1013 is set to mode 0. The time when the detection signal 110 is 1 means the time when the subsequent load instruction 107 waits due to the cache fill by the prefetch instruction 105.

  Specifically, the selector 1012 outputs the differentiation circuit output signal 114 to the counter 1010 when the mode of the differentiation circuit valid mode 1013 is mode 1, and the detection signal 110 when the mode of the differentiation circuit valid mode 1013 is mode 0. Is output to the timer 1014.

  The counter 1010 has a function of counting, and when the value 1 differentiating circuit output signal 114 is input, the counter 1010 increments by one.

  The timer 1014 has a function of measuring time, starts time measurement when a detection signal 110 having a value 1 is input, and ends time measurement when a detection signal 110 having a value 0 is input.

  The arithmetic unit 11 has a function of making the out-of-order execution condition between the load instruction 107 and another load instruction 107b equal to the out-of-order execution condition between the prefetch instruction 105 and the load instruction 107. Have.

  The arithmetic unit 11 has a configuration in which the prefetch instruction 105 does not overtake the preceding load instruction 107c that is not executed due to a shortage of resources in the main storage device 13 in the pipeline.

  The above-described out-of-order execution conditions and the configuration that does not overtake in the pipeline are well known to those skilled in the art of the present invention, and the details of the method are not directly related to the present invention. Is omitted.

  In addition, the present embodiment preferably includes a configuration that does not pass in the above-described pipeline, but even if it is not provided, the characteristics of the present invention are not impaired.

  In addition, the instruction issue control part, the register part, and the like which are not illustrated in the arithmetic unit 11 are not claimed by the present invention, and can be designed by those skilled in the art, and thus description thereof is omitted in the present invention.

  The counter 1010 and the timer 1014 have an instruction issue control part, a register part and an input / output, but are not claimed by the present invention and can be easily designed by those skilled in the art. Description is omitted.

(Description of the operation of the first embodiment)
Next, the operation of the present embodiment will be described in detail with reference to the drawings.

(Description of cache search operation)
First, the cache search operation according to the present embodiment will be described with reference to the flowcharts shown in FIGS.

  When the cache device 12 receives the prefetch instruction 105 or the load instruction 107 (step S401), it creates a search address that combines the index 1001 of the instruction address section 60 and the offset 1002 (step S402).

  Next, the cache device 12 performs a cache search using the search address as a key (step S403).

  As a result of the cache search, if the corresponding cache entry 113 exists (step S404 “YES”), the tag 1000 in the instruction address portion 60 and the cache tag portion 1007 in the cache entry 113 are located at positions corresponding to the tag 1000. The addresses are compared (step S405). Hereinafter, this operation is referred to as tag comparison.

As a result of the tag comparison, if the tags match (step S406 “YES”), a cache hit occurs (step S407).

  If the corresponding cache entry 113 does not exist as a result of the cache search (step S404 “NO”), or if the corresponding cache entry 113 exists as a result of the search address search, but does not match in the tag comparison (Step S404 “YES”, Step S406 “NO”) results in a cache miss (Step S408).

(Description of operation when prefetch instruction is issued)
Next, operations from sending the instruction fit 100 to sending the prefetch instruction 106 will be described with reference to the flowchart shown in FIG. It is assumed that the instruction code 301 is already stored in the main storage device 13.

  First, the arithmetic unit 11 sends the instruction fetch 100 to the cache unit 12 (step S501).

  When the cache device 12 receives the instruction fetch 100, the cache device 12 sends the instruction fetch 101 to the main storage device 13 (step S502).

  When the main storage device 13 receives the instruction fetch 101, it sends the instruction code 103 to the cache device 12 (step S503).

  When the cache device 12 receives the instruction code 103, the cache device 12 sends the instruction code 104 to the arithmetic device 11 (step S504).

  When the arithmetic unit 11 receives the instruction code 104, the arithmetic unit 11 starts executing the instruction code 104. The arithmetic unit 11 executes the instruction sequence of the instruction code 104 in order.

  If the execution line of the instruction code 104 is a prefetch instruction, the arithmetic unit 11 sends the prefetch instruction 105 to the cache device 12 (step S505).

  When the cache device 12 receives the prefetch instruction 105, it performs a cache search. If the cache search results in a cache hit (step S506 “YES”), the cache device 12 checks the valid flag 1004 (step S509).

  If the value of the valid flag 1004 is 0 (step S509 “0”), that is, if the cache entry 113 having a cache hit is being prefetched, the cache fill flag indicates that the cache fill has not been completed. 1 is set to 1005 (step S510), and then the prefetch instruction 105 is invalidated (step S511).

  If the value of the valid flag 1004 is 1 (step S509 “1”), that is, if the cache entry 113 having a cache hit is not being prefetched, the data requested by the prefetch instruction 105 is already in the cache entry 113. Therefore, the cache device 12 invalidates the prefetch instruction 105 (step S511).

  If the cache search results in a cache miss ("NO" in step S506), the cache device 12 sends the prefetch instruction 106 to the main storage device 13 (step S508).

  Since the present invention measures the number of times the subsequent load instruction 107 refers to the cache entry in the cache fill by the prefetch instruction 105 and the time that the load instruction 107 waits until the cache fill is completed. In the operation of the prefetch instruction described above, the prefetch instruction 106 is sent to the main storage device 13 due to a cache miss (step S508), and then the load instruction 107 is issued before the cache fill by the prefetch instruction 106 is completed. Will be described.

(Explanation of operation when load instruction is issued during cache fill)
Next, in the description of the operation of the prefetch instruction described above, after the prefetch instruction 106 is sent to the main storage device 13 due to a cache miss (step S508), the load instruction 107 is sent before the cache fill by the prefetch instruction 106 is completed. The operation in this case will be described with reference to the flowchart shown in FIG.

As a premise, the valid flag 1004 is 0 and the cache fill flag 1005 is 1 as shown in step S507 of FIG. The addresses indicated by the prefetch instruction 105 and the load instruction 107 are the same.

  If the execution line of the instruction code 103 is a load instruction, the arithmetic unit 11 sends the load instruction 107 to the cache device 12 (step S601).

  When the cache device 12 receives the load instruction 107, it performs a cache search.

  If the cache search results in a cache miss (step S602 “NO”), the cache device 12 sends the load instruction 108 to the main storage device 13 (step S603). In this case, the present invention is not claimed, and those skilled in the technical field of the present invention can easily analogize the operation.

  As a result of the cache search, if a cache hit occurs (step S602 “YES”), the cache device 12 checks the valid flag 1004 (step S604).

  If the value of the valid flag 1004 is 1 (step S604 “1”), that is, if the corresponding cache entry 113 specified by the load instruction 107 has a cache hit and no prefetch is performed, the load instruction Since the data requested in 107 is already in the cache entry 113, the cache device 12 sends the cache entry 113 to the arithmetic device 11 as the load data 112 (step S605).

  If the value of the valid flag 1004 is 0 (step S604 “0”), that is, the corresponding cache entry 113 specified by the load instruction 107 has a cache hit, but the prefetch is being executed, the cache device 12 With reference to the cache fill flag 1005, it is confirmed whether or not the cache entry 113 is in the middle of the cache fill.

  When the cache fill flag 1005 is 1 (step S606 “1”), that is, when the cache entry 113 is in the middle of the cache fill, the detection signal generation unit 1006 sets 1 to the detection signal 110 ( In step S607), the detection signal 110 is sent to the arithmetic unit 11 (step S608). Then, the cache device 12 waits for the load instruction 107 and waits for the arrival of the prefetch data 109 (step S610).

  Next, when the cache device 12 receives the prefetch data 109 from the main storage device 13 (step S609, step S610 “YES”), the cache device 12 cache-fills the prefetch data 109 to the cache entry 113 and sets 1 to the valid flag 1004. (Step S611).

  Further, the cache device 12 sets 0 to the cache fill flag 1005 (step S612).

  The detection signal generation unit 1006 sets 0 to the detection signal 110 (step S613), and sends the detection signal 110 to the arithmetic device 11 (step S614).

  Then, the cache device 12 sends the data in the cache entry 113 to the arithmetic device 51 as the load data 112 (step S615).

  Note that although it is conceivable that the load data 111 is received in step S609, the operation in that case is not claimed by the present invention, and those skilled in the art of the present invention can easily analogize the operation. Since it is a thing, description is abbreviate | omitted.

(Explanation of operation of arithmetic unit at detection signal reception)
Next, the operation of the arithmetic unit 11 when receiving the detection signal 110 will be described with reference to the flowchart shown in FIG.

  First, when the arithmetic device 11 receives the detection signal 110 sent from the cache device 12 in step S608 and step S614 of FIG. 6 (step S701), the arithmetic device 11 sends the detection signal 110 to the differentiation circuit 1011 and the selector 1012. Input (step S702).

  When the detection signal 110 is input, the differentiation circuit 1011 outputs a differentiation circuit output signal 114 that is a differential signal of the input detection signal 110 to the selector 1012 (step S703).

  Next, the selector 1012 outputs either the detection signal 110 input from the arithmetic unit 11 or the differentiation circuit output signal 114 input from the differentiation circuit 1011 according to the differentiation circuit valid mode 1013 (step S704).

  When the differentiation circuit valid mode 1013 is mode 1 (step S704 “mode 1”), the selector 1012 outputs the differentiation circuit output signal 114 to the counter 1010 (step S705).

  Next, the counter 1010 confirms the value of the input differentiation circuit output signal 114 (step S706).

  When the value of the differentiation circuit output signal 114 is 1 (step S706 "1"), the counter 1010 increments its counter by +1. (Step S709).

  When the differentiation circuit valid mode 1013 is mode 0 (step S704 "mode 0"), the selector 1012 outputs the detection signal 110 to the timer 1014 (step S708).

  Next, the timer 1014 confirms the value of the input detection signal 110 (step S709).

  When the value of the detection signal 110 is 1 (step S709 “1”), the timer 1014 starts time measurement (step S710).

  When the value of the detection signal 110 is 0 (step S709 “0”), the timer 1014 ends the time measurement (step S711).

  Note that the values of the counter 1010 and the timer 1014 are provided to the outside by the arithmetic unit 11. The timing to provide can be freely set, but is preferably provided when the execution of the instruction code 103 is completed, and the values of the counter 1010 and the timer 1014 are preferably reset at the time of provision.

(Effects of the first embodiment)
Next, the effect of this embodiment will be described.

  According to the present embodiment, it is possible to provide a user who creates a program with the number of times that the load instruction is delayed during execution of the cache fill based on the preceding prefetch instruction and the delay time.

  The reason is that the counter 1010 counts the number of times that the load instruction refers to the cache entry during cache fill execution based on the preceding prefetch instruction, and the time from the reference to the end of the cache fill, that is, load This is because the timer 1014 measures the time that the instruction waits for execution of the cache fill based on the prefetch instruction.

  The user who creates the program can refer to the reference count and the waiting time of the counter 1010 and the timer 1014, determine whether the insertion position of the prefetch instruction is appropriate, and correct the timing at which the prefetch instruction is executed.

  Specifically, when the values of the counter 1010 and the timer 1014 are large, the user who creates the program sets the position at which the prefetch instruction is executed so that the compiler 30 inserts the prefetch instruction at an earlier position in the instruction code 104. The execution performance of the information processing apparatus 10 can be improved by correcting the information.

  Next, a hardware configuration example of the computer system 10 of the present invention will be described with reference to FIG. FIG. 8 is a block diagram illustrating a hardware configuration example of the computer system 10.

  Referring to FIG. 8, a computer system 10 has a hardware configuration similar to that of a general computer device, and includes a data work area including memories such as a CPU (Central Processing Unit) 801 and a RAM (Random Access Memory). A main storage unit 802 used for a temporary data saving area, a communication unit 803 that transmits / receives data via a network, and an input / output interface unit that transmits / receives data by connecting to the input device 805, the output device 806, and the storage device 807 804, a system bus 808 for connecting the above-described components to each other is provided. The storage device 807 is realized by, for example, a hard disk device including a non-volatile memory such as a ROM (Read Only Memory), a magnetic disk, and a semiconductor memory.

  The information processing apparatus 100 and the compile processing apparatus 20 of the computer system 10 of the present invention are mounted on a circuit component, which is a hardware component such as an LSI (Large Scale Integration), in which a program is incorporated. As a matter of course, it is also possible to realize a software program by storing a program providing the function in the storage device 807, loading the program into the main storage unit 802, and executing it by the CPU 801. is there.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments, and various modifications can be made within the scope of the technical idea. .

1: Computer system 10: Information processing device 11: Arithmetic device 12: Cache device 13: Main storage device 100, 101: Instruction fits 103, 104, 301: Instruction code 105, 106: Prefetch instructions 107, 107b, 107c, 108: Load instruction 109: Prefetch data 110: Detection signal 111, 112: Load data 113: Cache entry 114: Differentiation circuit output signal 1000: Tag 1001: Index 1002: Offset 1003: Instruction address 1004: Valid flag 1005: Cache fill flag 1006: Detection signal generation unit 1007: Cache tag unit 1008: Cache data unit 1010: Counter 1011: Differentiation circuit 1012: Selector 1013: Differentiation circuit valid mode 1 14: timer 20: program code 30: compiler

Claims (15)

An information processing apparatus including an arithmetic device, a main storage device, and a cache device,
Information processing having a function of detecting a load instruction for the cache apparatus that has been delayed due to execution of a cache fill by a prefetch instruction from the arithmetic unit and acquiring the number of occurrences or duration of the detected load instruction apparatus. The cache device includes a delay detection unit that detects the load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction,
2. The information processing apparatus according to claim 1, wherein the arithmetic unit includes a counter that counts the number of occurrences of the load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction detected by the delay detection unit. . The delay detection means of the cache device,
When the load instruction having a cache hit refers to an entry that is being cache-filled by a prefetch instruction, the load instruction is detected as a load instruction that is delayed due to a cache-fill execution by a prefetch instruction. The information processing apparatus according to claim 2, wherein a detection signal is output to the counting means. Each entry of the cache device is provided with a flag indicating whether each entry is executing cache fill and a flag indicating whether each entry is executing prefetch,
The delay detecting means refers to the entry indicating that the load instruction is executing the cache fill by the prefetch instruction based on the flag indicating whether the cache fill is being executed and the flag indicating whether the prefetch is being executed. The information processing apparatus according to claim 3, wherein the information processing apparatus detects whether it has been performed. A timer for measuring a duration of a detection signal from a delay detection unit of the cache device;
5. The information processing according to claim 1, further comprising a selector that selectively outputs a detection signal from the delay detection unit to the counter or the timer based on a setting mode. apparatus. A load instruction delay determination method in an information processing device including an arithmetic device, a main storage device, and a cache device,
Detecting a load instruction for the cache device in which a delay has occurred during execution of a cache fill by a prefetch instruction from the arithmetic device;
A method for determining a delay of a load instruction, comprising: obtaining the number of occurrences or duration of the detected load instruction. A delay detecting step of detecting the load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction by the cache device;
7. The load instruction according to claim 6, further comprising a step of counting the number of occurrences of the load instruction in which a delay has occurred during execution of a cache fill by the prefetch instruction detected in the delay detection step by the arithmetic unit. Delay judgment method. In the delay detection step,
When the load instruction having a cache hit refers to an entry in which a cache fill is being executed by a prefetch instruction, the load instruction is detected as a load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction, and 8. The load instruction delay determination method according to claim 7, wherein a detection signal is output. Each entry of the cache device is provided with a flag indicating whether each entry is executing cache fill and a flag indicating whether each entry is executing prefetch,
In the delay detection step, the load instruction refers to an entry in which the cache fill is being executed by the prefetch instruction based on the flag indicating whether the cache fill is being executed and the flag indicating whether the prefetch is being executed. 9. The load instruction delay determining method according to claim 8, wherein whether or not the load instruction has been detected is detected. The arithmetic unit is
Measuring the duration of the detection signal from the delay detection means of the cache device;
10. The load instruction according to claim 6, further comprising a step of selectively outputting a detection signal from the delay detection means to the counter or the timer based on a setting mode. Delay judgment method. A load instruction delay determination program executed by an information processing device including an arithmetic device, a main storage device, and a cache device,
A function for detecting a load instruction for the cache device that has been delayed due to a cache fill being executed by a prefetch instruction from the arithmetic unit;
A load instruction delay determination program which causes the information processing apparatus to execute a function of acquiring the number of occurrences or duration of the detected load instruction. Causing the cache device to execute a delay detection function for detecting the occurrence of the load instruction that has been delayed due to a cache fill being executed by a prefetch instruction;
12. The load instruction according to claim 11, wherein the arithmetic unit is caused to execute a function of counting the number of occurrences of the load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction detected by the delay detection function. Delay judgment program. With the delay detection function,
When the load instruction having a cache hit refers to an entry in which a cache fill is being executed by a prefetch instruction, the load instruction is detected as a load instruction in which a delay has occurred during execution of a cache fill by a prefetch instruction, and 13. The load instruction delay determination program according to claim 12, wherein a detection signal is output. Each entry of the cache device is provided with a flag indicating whether each entry is executing cache fill and a flag indicating whether each entry is executing prefetch,
In the delay detection function, the load instruction referred to an entry in the cache fill execution by the prefetch instruction based on the flag indicating whether the cache fill is being executed and the flag indicating whether the prefetch is being executed. 14. The load instruction delay determination program according to claim 13, wherein the load instruction delay determination program according to claim 13 is detected. In the arithmetic unit,
A function of measuring the duration of the detection signal from the delay detection function of the cache device;
The load according to any one of claims 11 to 14, wherein a function of selectively outputting a detection signal from the delay detection means to the counter or the timer based on a setting mode is executed. Instruction delay judgment program.

Images