JPS63110946U - - Google Patents

Info

Publication number
JPS63110946U
JPS63110946U JP18911087U JP18911087U JPS63110946U JP S63110946 U JPS63110946 U JP S63110946U JP 18911087 U JP18911087 U JP 18911087U JP 18911087 U JP18911087 U JP 18911087U JP S63110946 U JPS63110946 U JP S63110946U
Authority
JP
Japan
Prior art keywords
request
data
buffer memory
storage device
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18911087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18911087U priority Critical patent/JPS63110946U/ja
Publication of JPS63110946U publication Critical patent/JPS63110946U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はパイプライン方式で処理されるバツフ
アメモリを有する処理装置に於けるバツフアメモ
リと主記憶装置間のデータ転送に係るタイムチヤ
ートを示し、バツフアメモリのリクエストに対す
るデータ不在が連続的に発生する状況に対する従
来技術をaに、本考案をbに示す。第2図は本考
案の回路構成を系統図にて示すものである。 第2図において、10はレジスタEAR、12
はバツフアメモリ、13はレジスタOWR、16
はMSAR、18はPF PORTである。
Figure 1 shows a time chart related to data transfer between the buffer memory and the main memory in a processing device having a buffer memory that is processed in a pipeline method. The technique is shown in a, and the invention is shown in b. FIG. 2 is a system diagram showing the circuit configuration of the present invention. In FIG. 2, 10 is the register EAR, 12
is buffer memory, 13 is register OWR, 16
is MSAR, and 18 is PF PORT.

Claims (1)

【実用新案登録請求の範囲】 主記憶装置とバツフアメモリとを有しパイプラ
イン方式によりデータ処理を行う処理装置であつ
て、 先行リクエストにより前記バツフアメモリをア
クセスし、データ不在のため主記憶装置よりのデ
ータ転送を要求中、後続リクエストにより前記バ
ツフアメモリのアクセスが発生した場合、 前記先行リクエストによるデータ転送の完了を
待つことなく、前記後続リクエストの要求する前
バツフアメモリ内のデータの在否を調べ、 データが存在した場合は前記後続リクエストを
一旦キヤンセルし、前記先行リクエストによるデ
ータ転送の完了後、前記後続リクエストにより再
び前記バツフアメモリをアクセスすることにより
処理を進行するバツフアメモリの制御回路におい
て、 前記データが不在の場合は、リクエストアドレ
スを保持して該主記憶装置に対しデータ転送要求
を出すリクエスト保持レジスタを設けたことを特
徴とするプリフエツチ制御回路。
[Claims for Utility Model Registration] A processing device that has a main storage device and a buffer memory and performs data processing using a pipeline method, wherein the buffer memory is accessed by a preceding request, and data is transferred from the main storage device due to the absence of data. If the buffer memory is accessed by a subsequent request during a transfer request, without waiting for the completion of the data transfer by the preceding request, the presence or absence of the data requested by the subsequent request in the previous buffer memory is checked and the existence of the data is determined. If the data is absent, the buffer memory control circuit cancels the subsequent request, and after the completion of the data transfer by the preceding request, accesses the buffer memory again by the subsequent request to proceed with the process. . A prefetch control circuit comprising a request holding register that holds a request address and issues a data transfer request to the main storage device.
JP18911087U 1987-12-10 1987-12-10 Pending JPS63110946U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18911087U JPS63110946U (en) 1987-12-10 1987-12-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18911087U JPS63110946U (en) 1987-12-10 1987-12-10

Publications (1)

Publication Number Publication Date
JPS63110946U true JPS63110946U (en) 1988-07-16

Family

ID=31141108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18911087U Pending JPS63110946U (en) 1987-12-10 1987-12-10

Country Status (1)

Country Link
JP (1) JPS63110946U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5096143A (en) * 1973-12-24 1975-07-31
JPS5293243A (en) * 1976-01-31 1977-08-05 Nec Corp Data processing unit performing preceding control
JPS5475964A (en) * 1977-11-30 1979-06-18 Toshiba Corp Data pre-fetch system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5096143A (en) * 1973-12-24 1975-07-31
JPS5293243A (en) * 1976-01-31 1977-08-05 Nec Corp Data processing unit performing preceding control
JPS5475964A (en) * 1977-11-30 1979-06-18 Toshiba Corp Data pre-fetch system

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