JPH01258153A - Block data transfer system for cache memory - Google Patents

Abstract

PURPOSE:To shorten the use time of a bus by transferring continuous data which starts with data, which a processor requests, and is stored in a preliminarily determined address direction at the time of transferring block data from a main memory to a cache memory. CONSTITUTION:When block data including sub-block data which a processor 1 requests is transferred from a main memory 4 to a cache memory 2 because sub-block data which the processor 1 requests does not exist on the cache memory 2, continuous data which starts with sub-block data which the processor requests out of sub-block data included in block data and is stored in a preliminarily determined address direction is transferred from the main memory 4 to the cache memory 2. Thus, the bus is prevented from being used for transfer of unnecessary data to shorten the use time of the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device comprising a processor, a main memory, and a cache memory, and particularly relates to a cache memory block data transfer method (prior art). A memory block data transfer method will be explained with reference to FIG.

FIG. 2 is a block diagram for explaining the conventional technology,
1 is a processor, 2 is a cache memory, 3 is a bus, 4
is the main memory. The data on main memory 4 is
It is divided into a plurality of block data of equal size, and each block data is further divided into a plurality of sub-block data of equal size. 21st! ! In 1, one block data consists of four sub-block data.

The cache memory 2 is a memory section 21 that can store a plurality of block data, and a tag memory section 22 that stores address information of block data in the memory section 21.
, a valid memory section 23 that indicates whether each sub-block data in the block data in the memory section 21 is valid (rlJ) or invalid (ro''). It is assumed that bus 3 transfers one sub-block data in one bus cycle.

The sub-block data requested by the processor 1 to the cache memory 2 via the signal line 101 is sent to the cache memory 2.
When the cache memory 2 does not exist in the memory unit 21 (miss), the cache memory 2 outputs a transfer request for the block data on the bus 3 and the address of the sub-block data via the signal line 201.

Note that whether or not the target data already exists in the cache memory 2 is determined by searching the tag memory section 22. When the data address is received, all sub-block data of the block data including the designated sub-block data are read out and sequentially output onto the bus 3 via the signal line 401. The cache memory 2 writes the address information of the block data into a predetermined column of the tag memory section 22, and repeats the following operation for every sub-block data in the block data.

(1) Receive sub-block data on the bus 3 via the signal line 201, and transfer the sub-block data to the memory unit 21.
write to the specified column of .

(2) Set the bit corresponding to the sub-block data in a predetermined column of the valid bit memory section 23 to "1".

The cache memory 2 includes a valid pit memory section 2 corresponding to sub-block data requested by the processor 1.
When the corresponding bit of 3 becomes "1", the sub-block data is transferred to the processor 1 via the signal line 101.

[Problem to be solved by the invention]

In the conventional method described above, when a cache memory miss occurs, all sub-block data included in the block data to which the sub-block data requested by the processor belongs is transferred from the main memory to the cache memory. However, within the shell, the addresses of sub-block data that the processor requests from the cache memory are fixed in one direction.

Of the sub-block data included in the block data, the sub-block data in the opposite direction from the sub-block data requested by the processor is often not requested by the processor after that, and in the conventional method, meaningless sub-block data is There was also a problem in that the bus was occupied during transfer, increasing the bus usage time.

For example, suppose that subblock data 1 to 4 are stored in the main memory 4 as shown in FIG. 3, and subblock data 3 requested by the processor is stored in the main memory in the direction of increasing addresses. . When the processor requests the sub-block data 3 and causes a miss in the cache memory, in the conventional method, all sub-block data 1 to 4 in the corresponding block data are transferred to the cache memory via the bus. 1
Sub-block data such as sub-block data 2 and sub-block data 2 which are no longer needed are also transferred, and the bus is occupied until the transfer of all these sub-block data is completed.

An object of the present invention is to eliminate unnecessary transfer of sub-block data from main memory to cache memory and to shorten bus usage time.

[Means to solve the problem]

In the present invention, when sub-block data requested by a processor does not exist on the cache memory and block data including the sub-block data requested by the processor is transferred from main memory to cache memory, sub-block data included in the block data is transferred from main memory to cache memory. It is characterized by starting with the sub-block data requested by the processor from among the block data, and transferring consecutive sub-block data stored in the direction of a predetermined address in the main memory from the main memory to the cache memory. .

(Function) In the present invention, among the block data in the main memory, only consecutive sub-block data in a predetermined address direction starting with the sub-block data requested by the processor are transferred to the cache memory. It is possible to prevent the bus from being used for transferring unnecessary sub-block data, and the bus usage time is shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating an embodiment of the block data transfer method of the present invention, in which 1 is a processor, 2 is a cache memory, 3 is a bus, and 4 is a main memory. The data on the main memory 4 is divided into a plurality of block data, and each block data is further divided into a plurality of sub-block data. In Figure 1, as in Figure 2, 1
It is assumed that one block data consists of four sub-block data. 21 is a memory section that can store a plurality of block data; 22 is a tag memory section that stores address information of the block data in the memory section 21 of the cache memory 2; and 23 is a tag memory section that is stored in the memory section 21. Validity of sub-block data within block data (rl
), a valid bit memory section indicating invalidity (rOJ). It is assumed that bus 3 transfers one sub-block data in one bus cycle. It is also assumed that the sub-block data requested by the processor 1 are stored in the main memory 4 in the direction of increasing addresses.

Processor 1 communicates with cache memory 2 via signal 101.
When the requested sub-block data does not exist in the memory section 21 of the cache memory 2 (you can find out whether it exists or not by searching the tag memory section 23), the cache memory 2
outputs a block data transfer request and sub-block data address onto the bus 3 via the signal line 201. Main memory 4 receives a transfer request for block data on bus 3 and an address for sub-block data via signal line 401. Then, the main memory 4 reads the sub-block data in the increasing direction of the specified sub-block data address from among the block data including the specified sub-block data, and transfers it onto the bus 3 via the signal line 401. Output sequentially. The cache memory 2 writes the address information of the block data into a predetermined column of the tag memory section 22, and performs the following operations for each sub-block data in the increasing address direction from the sub-block data requested by the processor 1 included in the block data. Repeat.

(1) Receive sub-block data on the bus 3 via the signal line 201 and transfer the sub-block data to the memory 201.
at a predetermined position in a predetermined column of the section.

(2) Set the bit corresponding to the corresponding sub-block data in a predetermined column of the valid pit memory section 23 to [1].

The cache memory 2 transmits a signal to the signal line 10 when the corresponding bit of the valid pit memory section 23 corresponding to the sub-block data requested by the processor 1 becomes "1".
1 to the processor 1.

In the present invention, in the example shown in FIG. 3, only sub-block data 3 and 4 in the block data of the main memory 4 are stored in the corresponding column of the memory section 21 of the cache memory 2. 1st L! ! ro of the valid pit memory section 23 of l
ollJ shows this state.

〔Effect of the invention〕

As described above, according to the present invention, sub-block data that is not used by the processor is not transferred, so that the bus usage time can be shortened. Therefore, by using the method of the present invention, even if the size of block data is increased.

The bus usage time does not increase due to the transfer of data not requested by the processor, as in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a block diagram for explaining a conventional system, and FIG. 3 is a block diagram for explaining an embodiment of the present invention.
The figure shows the relationship between data in the main memory and address directions. 1... Processor, 2... Cache memory,
3... Bus, 4... Main memory, 21... Memory section, 22... Tag memory section, 23... Valid pit memory section.

Claims (1)

[Claims] (1) In an information processing device consisting of a processor, a main memory, and a cache memory that stores part of the data in the main memory, the data requested by the processor does not exist in the cache memory, and the data requested by the processor is When transferring block data containing data from the main memory to the cache memory, starting with the data requested by the processor, continuous data stored in the main memory in the direction of a predetermined address is transferred to the cache memory. A cache memory block data transfer method characterized by transferring data from a main memory to the cache memory.