JPS5764860A - Parallel processing system - Google Patents

Parallel processing system

Info

Publication number
JPS5764860A
JPS5764860A JP14132480A JP14132480A JPS5764860A JP S5764860 A JPS5764860 A JP S5764860A JP 14132480 A JP14132480 A JP 14132480A JP 14132480 A JP14132480 A JP 14132480A JP S5764860 A JPS5764860 A JP S5764860A
Authority
JP
Japan
Prior art keywords
command
register
held
address
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14132480A
Other languages
Japanese (ja)
Other versions
JPS6150359B2 (en
Inventor
Sada Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14132480A priority Critical patent/JPS5764860A/en
Publication of JPS5764860A publication Critical patent/JPS5764860A/en
Publication of JPS6150359B2 publication Critical patent/JPS6150359B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To decrease the transfer frequency of the control information and to increase the performance, by securing such a constitution in that each processor obtains the executing frequency necessary for a command as well as the storing location of the data necessary for execution by the command that is given once from a controller. CONSTITUTION:Each of the processors that constitute a parallel processor receives a command at its command register CR from a controller CU, decodes the command and at the same time gives an access to a control storage CM designated by the command. Then a series of microinstructions are read out of an address to a microinstruction register MIR to perform an operation. The addition/subtraction, shift and logic operation are carried out by an arithmetic unit ALU. The result of operation is held at an accumulator ACC. At the same time, the address for communication to be given to a memory or another processor is held at an address register MAR, and the data sent from other processor are held at a register MDR respectively.
JP14132480A 1980-10-09 1980-10-09 Parallel processing system Granted JPS5764860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14132480A JPS5764860A (en) 1980-10-09 1980-10-09 Parallel processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14132480A JPS5764860A (en) 1980-10-09 1980-10-09 Parallel processing system

Publications (2)

Publication Number Publication Date
JPS5764860A true JPS5764860A (en) 1982-04-20
JPS6150359B2 JPS6150359B2 (en) 1986-11-04

Family

ID=15289270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14132480A Granted JPS5764860A (en) 1980-10-09 1980-10-09 Parallel processing system

Country Status (1)

Country Link
JP (1) JPS5764860A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186848A (en) * 1982-04-23 1983-10-31 Oki Electric Ind Co Ltd Data flow processing system
JPS58203571A (en) * 1982-05-21 1983-11-28 Hitachi Ltd Device for forming picture
JPS6226579A (en) * 1985-07-26 1987-02-04 Nec Corp Vector sum-total arithmetic unit
EP0386151A1 (en) * 1987-11-10 1990-09-12 Echelon Systems Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control.
JPH07129521A (en) * 1993-01-11 1995-05-19 Nec Corp Parallel processing system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04225449A (en) * 1990-12-27 1992-08-14 Nec Eng Ltd Fault detection processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186848A (en) * 1982-04-23 1983-10-31 Oki Electric Ind Co Ltd Data flow processing system
JPS58203571A (en) * 1982-05-21 1983-11-28 Hitachi Ltd Device for forming picture
JPS6226579A (en) * 1985-07-26 1987-02-04 Nec Corp Vector sum-total arithmetic unit
EP0386151A1 (en) * 1987-11-10 1990-09-12 Echelon Systems Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control.
JPH07129521A (en) * 1993-01-11 1995-05-19 Nec Corp Parallel processing system

Also Published As

Publication number Publication date
JPS6150359B2 (en) 1986-11-04

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