JPS6226579A - Vector sum-total arithmetic unit - Google Patents

Abstract

PURPOSE:To have the constitution to add corresponding to the vector element between usual vectors and to calculate the sum-total of the element of the vector by one instruction by providing plural output means, the calculating means and the selecting means of the vector storing means. CONSTITUTION:When for example, a vector A of the number 8 of the element is set to a vector storing means 10, an index 3 of 2<3> is set to a -1 counter 86. From a decoder 87, the number 2<3-1> of the effective vector element of the vector adding action is outputted. The vector storing means 10 outputs data a0 of the '0' address from the first output means 11 and data a1 of the first address from the second output means 14 as the first vector element. At selecting means 40 and 60, the vector element is selected and given to a vector adding means 70. The vector of the adding result is set to the vector storing means 10. Simultaneously, the -1 counter 86 executes the counting and the counter value is updated to '2'.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vector calculation device, and more particularly to a calculation device that performs a summation calculation of vector elements.

2. Description of the Related Art In general, vector calculation devices are configured to perform element-corresponding calculations between a plurality of vectors. Therefore, when calculating the sum of one vector, since the operation is performed on seven vectors, it is necessary to provide a special addition means and its control means in addition to the usual addition means corresponding to vector elements, or to use ordinary vector elements. In order to use the corresponding vector addition means, 1/2 of the elements of the vector for which one summation is to be obtained are stored in one vector storage means, normal vector addition is performed, and the elements of the vector resulting from the addition are stored 1/2 at a time. It was necessary to repeat the operation of storing the vectors separately in one vector storage means and performing vector addition until the summation result of the vector had one element.

Problems to be Solved by the Invention As a result, in the former method, the hardware of the arithmetic unit becomes large and the control of the vector arithmetic unit as a whole becomes complicated, whereas in the latter method, all operations are performed using ordinary vector addition means. This can be done with software, but it takes a lot of time to process other than vector addition, such as storing the elements of one vector in each A vector and 2 operations, which increases the overall processing time. There was a drawback.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology. Therefore, an object of the present invention is to provide a simple vector addition system which has a configuration that can also perform addition corresponding to vector elements. An object of the present invention is to provide a novel vector summation calculation device that can calculate the summation of vector elements with one instruction without causing performance deterioration due to configuration.

Means for Solving the Problems In order to achieve the above object, the vector sum calculation device according to the present invention is capable of storing a vector having N pieces of data as elements and simultaneously outputting a plurality of different arbitrary vector elements. vector storage means that includes a plurality of output means that are assumed to be 1, a vector addition means that receives and adds the plurality of vector elements, and a vector addition means that calculates the total sum and calculates the summation of the vector element addition operation from the number of effective vector elements of the vector. It is configured to include a calculation means for calculating the number of effective vector elements based on the number of repetitions and each vector addition operation.

EXAMPLES Hereinafter, preferred embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 7 is a block diagram showing an embodiment of the present invention. This embodiment has vector storage means 10 and 20° JO, each of which includes first output means //, 2/, and 3/, respectively, and only the vector storage means IO includes a third output means LLI. This first output means //, 2/
, 3/ are respectively transferred to the selection means q-o, , to through the data bus /co, /j IW, N+32.33, and one of them is selected. Here, regarding the selection means, the selected vector elements are transferred to the vector addition means 70 through the data bus, but the vector elements selected by the selection means SO are transferred to the selection means 60 through the data bus &/; In the means 6o, the second output means /lL1 of the vector storage means 10
Then, one of the vector elements to be transferred through the data bus /S is selected.

The vector addition means 70Vc is transferred through the data bus 61. The control is performed by the control bus daco, 5co, and luco, and when seeking moderation of the vector elements, the vector element outputted from the first output means // of the vector storage means 10 is selected in the selection means violation. Similarly, the means 60 selects the vector element output from the output means/II of the vector storage means 10.

The vector addition means 70 receives one of these vector elements, performs the addition, and transfers the addition result vector to the data bus 7.
/ through the vector storage means 10.2t), 30. When calculating the sum of the elements of a vector, the vector resulting from the addition is set in vector storage means 10K, which is the vector storage means in which the vector for which the sum is to be calculated is set.

The calculation means go is based on the control buses 1/, 1, and 3. Has tda. Control bus 1/ is used for vector addition when calculating the sum of vector elements. Vector storage means 10 for storing the number of valid vector elements of the operation. The vector addition means 70 is supplied with the vector addition means 70 to perform addition corresponding to the vector elements according to the number of elements. The control bus g3 receives the end of the vector addition operation, and the control bus g3
receives the valid number of vector elements of the vector whose summation is desired, and the control bus Z1 outputs the completion of the vector summation operation.

Referring to FIG. 2, which is a block diagram of the calculation means 10,
Calculation means 10 is encoder 1! , -/counter 1&,
Decoder 17.0 includes a comparator a. The encoder gz is
Receiving the effective number of elements M of the vector whose summation is to be given from the control bus t3, M and -m are set in the -l counter 6, and the decoder t7 receives the value m of the -l counter 9f g6.
Yo! 72m/ is output as the effective number of vector elements for the vector addition operation through the control bus 1/. Also, the 0 comparator tg outputs to the control bus tllK whether the value of the -l counter 6 is 0OVa.

Next, the operation of this embodiment having the above configuration will be explained in detail. If the vector to be summed is a vector A having M elements, it is expressed as shown in FIG. Taking as an example the case where the number of vector elements is @tn, as shown in step l in FIG.
is set to 13''.The decoder S7 outputs the effective number of vector elements for the vector addition operation, and the vector addition operation is executed.At this time, the vector storage means 10 stores the number of vector elements as the first vector element. The first output means/l outputs the data a at the 0th address, and the co-output means/Hiro outputs the data a at the first address.

Thereafter, vector elements at consecutive addresses, such as bal and eLS, are output simultaneously as the second vector element. When the selection means is violated and 6θ, the 7th. The vector elements output from the output means //, /14 are selected and applied to the vector addition means 70. In the vector addition means 70, a vector addition operation is executed, and the vector resulting from the addition is set as shown in step 7 of FIG. v of the vector storage means 10K. At the same time, the counter g6 counts and the counter value is updated to -1 (here, a represents the addition result of vector elements a1 and -Jaj, and similarly, the addition result of al, j and ak17 shall be expressed as a, j, ni, etc.). Subsequently, in the same manner as before, the vector addition operation is repeatedly executed using the effective number of vector elements of the vector addition operation outputted from the decoder g7 until the value of the 1/counter t4 reaches "θ". As a result, as shown in step D in Fig. f, the sum of vectors A in this case is stored in the vector storage means io.
7 is set, the O comparator ttllc outputs through the control bus that the sum of the elements of the vector has been calculated, and the operation ends.

Up to this point, we have described an example in which only one vector storage means includes the first output means, as shown in FIG. Next, a case will be described in which all vector storage means include the first output means. FIG. S is a block configuration diagram showing an embodiment in that case. In the case of this embodiment, selection means 90 is added to select the vector element outputted by the first output means of the plurality of vector storage means, but its control is the same as that of the selection means Select the vector storage means in which the vector is stored. The other controls and operations are exactly the same as the embodiment shown in FIG. 1 described above.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the present invention provides a configuration in which the vector storage means has a plurality of output means, calculation means, and selection means, so that addition of vector elements corresponding to ordinary vectors can be performed. , − commands can be used to obtain the effect of calculating the sum of the elements of a vector. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.
The figures are block diagrams of the calculation means 10 in FIGS. 1 and S, FIG. 3 is a diagram of vectors for calculating the summation, and FIG. 5 are block diagrams showing other embodiments of the present invention. IQ, m, 30...vector storage means, //, /
Da, 2/, Yuq. 31.3 da...first or first output means, <u, s
o, to. 10... Selection means, 70... Vector addition means,
go... Calculation means, t5... Encoder %S6...
・-l counter, lr7...decoder, tza・0 comparator, /2. /3. /! , u, 2J. Total, 3 pieces, 7.7.3! r, 'II,! rl,
A/, ? /, ri/...data bus, 112. ! ;
Yu, 6, II/, g Yu, S31 cup... Control bus patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai 14: 2nd output stage 40, 50. 60: Eitan means No. Figure 1 Figure 2

Claims (3)

[Claims] (1) a vector storage means including a plurality of output means capable of storing a vector having N data as elements and outputting a plurality of different arbitrary vector elements at the same time;
A vector addition means that receives and adds the plurality of vector elements, and calculates the number of repetitions of the addition operation between vector elements and the number of effective vector elements in each vector addition operation from the number of effective vector elements of the vector for which the sum is to be obtained. 1. A vector summation calculation device, characterized in that it has a calculation means for calculating a summation of vector elements. (2) The vector sum calculation device according to claim 1, further comprising a selection means for switching the vector element outputs of the plurality of vector storage means and supplying the same to the vector addition means. (3) The patent further characterized in that the selection means has a function of giving different vector element outputs of the vector storage means to the vector addition means, and can also perform addition of vector elements corresponding to normal vectors. Claim No. 2
) The vector sum calculation device described in item 1.