JPH05334391A - Control circuit generating device - Google Patents

Abstract

PURPOSE:To generate an efficient control sequence by deciding whether or not an arithmetic node and a storage element node can share the same computing element and register and performing scheduling which utilizes the result. CONSTITUTION:This control circuit generating device has a control data flow graph reading device 2 which reads a control data flow graph 1 in, an execution condition code generating device 3 which grants the execution conditions of arithmetic in the graph to each arithmetic operation, a scheduling device 4 which schedules the respective arithmetic operations, and a control sequence generating device 5 which generates a control circuit 6. The control data flow graph 1 is read in by the control data flow graph reading device 2, the arithmetic execution condition code generating device 3 grants arithmetic execution condition codes to the respective arithmetic operations in conditional branches of the graph, and the control sequence generating circuit 5 generates control sequences, condition by condition, by utilizing the codes and outputs the control circuit for the output of the scheduling device 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for synthesizing a control circuit by deciding an operation sequence for the result of scheduling the operation of a control data flow graph representing the control of the operation of the circuit and the flow of data.

[0002]

2. Description of the Related Art A result of performing scheduling for determining the execution order of its operations and its execution step from a control data flow graph showing the flow of control and data becomes, for example, as shown in (1) of FIG. When executing this scheduling result, conventionally, a control circuit has been generated that sequentially executes the operation of each step as shown in (3) of FIG.

However, when the circuit operation indicated by the control data flow includes a conditional branch, the operation sequence obtained as described above has room for improvement. That is,
Depending on which condition of the conditional branch is satisfied, it may be possible to jump to the next operation step without executing the operation step.

Whether or not a certain operation step can be skipped depending on whether or not such a branch condition is satisfied can be obtained by analyzing the execution condition of each operation node. However, when the conditions are deeply nested and complicated, it takes a long time to calculate the conditions to be skipped.

[0005]

Therefore, in the above method, there is a problem in that a control circuit that performs an operation whose average execution speed is slow is generated, and the number of operations increases and the conditions are complicated. In this case, it takes a lot of time to find a control circuit that operates efficiently.

An object of the present invention is to eliminate such problems and to provide a control circuit which gives an efficient control sequence to the result of scheduling a control data flow graph having conditional branches. It is an object of the present invention to provide a control circuit generation device that can be generated in a calculation time proportional to.

Further, in the conventional method, since the control data flow graph is not explicitly shown and the exclusivity between the operations which cannot be found without analyzing the data dependency is not exclusive, the number of necessary arithmetic units is calculated to be large. There was a problem that it would be done.

A second object of the present invention is to provide a control circuit generator capable of giving a more efficient control sequence in consideration of exclusivity between operations not explicitly shown in the control data flow graph. Is to provide.

Further, in the conventional scheduling and parallelizing compiler, the scheduling in which the intra-branch operation is executed prior to the branch operation of the conditional branch has not been assumed. In such a case, the exclusivity of the operation dynamically changes depending on whether or not the conditional branch operation has been executed, but there is a problem that the control circuit cannot be obtained in consideration of such dynamic exclusivity. It was

A third object of the present invention is to provide a control circuit generation device capable of obtaining the required number of arithmetic units by utilizing such exclusivity between dynamic arithmetic operations.

[0011]

A control circuit generator according to the present invention generates a control circuit which is a result of scheduling a control data flow graph, which receives a control data flow graph representing control of circuit operation and data flow. A device, which is a control data flow graph reading device,
A control sequence for synthesizing an execution condition code generation device that receives the read control data flow graph, a scheduling device that performs scheduling by using the output of the execution condition code generation device, and a control device that controls the scheduled result. And a generator.

Further, the control circuit generator of the present invention derives the exclusivity between the operations which is not explicitly shown in the control data flow grab from the data dependency and generates the operation execution condition code indicating the exclusivity between the operations. A dependent execution condition code generation device is included.

Further, the control circuit generation device of the present invention generates an operation execution condition code indicating the exclusivity of the intra-branch operation which dynamically changes depending on whether the conditional judgment operation for determining the conditional branch is completed or not. And a dynamic execution condition code generation device for performing the same.

[0014]

According to the present invention, the control data flow graph is read by the control data flow graph reading device,
An operation execution condition code generator gives a later operation execution condition code to each operation in the conditional branch of the graph, and the control sequence generator generates a control sequence for each condition using the code, and controls Output the circuit.

Further, the control data flow graph is read by the control data flow graph reading device, and for each operation in the conditional branch of the graph, the operation execution condition code generation device explicitly sets the control data flow graph on the control data flow graph. Derives the execution conditions for the operations not shown,
An operation execution condition code indicating that is given, and the control sequence generation device generates a control sequence for each condition using this code, and outputs the control circuit.

Further, the control data flow graph is read by the control data flow graph reading device, and for each operation in the conditional branch of the graph, the operation execution condition code generator dynamically determines whether or not the conditional branch operation has been executed. The operation execution condition code indicating the exclusivity between the operations is changed, the control sequence generation device generates a control sequence for each condition by using this code, and outputs the control circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view showing a first embodiment of the present invention. In the figure, the control circuit generation device of the present invention comprises a control data flow graph reading device 2 for reading a control data flow graph 1, an execution condition code generation device 3 for giving an execution condition of an operation in the graph to each operation, Scheduling device 4 for scheduling computation and control circuit 6
And a control sequence generation device 5 for generating.

First, the control data flow graph 1 is read by the control data flow graph reading device 2. Execution of each operation by the execution condition code generation device 3 on each of the operation node and storage element node (hereinafter referred to as "register node") of the data flow graph, and the node indicating transfer of data (hereinafter referred to as "transfer node") A condition code (hereinafter referred to as “condition code”) is given. (Hereinafter, the operation node and the register node, and the transfer node can be treated in the same manner regarding the exclusivity analysis.
Transfer is simply referred to as operation, and the operation node represents a register node or a transfer node. ) The condition code is a code having the following properties and indicates the execution condition of the operation node, the register node, and the transfer node of the control data flow graph.

FIG. 4 is an explanatory diagram showing an example of the behavioral description and condition code, and FIG. 5 is an explanatory diagram showing the branch structure of FIG. Referring to the figure, in the condition code, the code is as long as the number of conditions that are the leaves of the conditional branch (the conditions corresponding to the leaves when the branch structure is viewed), and only one leaf condition is "1". Define to have. The branch structure of the behavioral description of FIG. 4 is as shown in FIG.
There are three branch leaves. Therefore, the condition code is 3 bits. In the figure, 1 is set from the left in order from the top, but the order is arbitrary.

As shown in FIG. 5, except the leaf condition, they are given by the logical sum of the signs of the child's condition (logical sum when the sign is considered as a vector). Condition codes corresponding to the respective operations (1) to (6) are shown in FIG.

The execution condition code generation device 3 gives the condition code thus determined to the node on the control data flow graph. From the definition, it can be seen that two condition codes are mutually exclusive when they do not have a '1' component in the same place. In that case, the nodes with the two condition codes are the same operator (or register, etc.). ) Can be shared.

FIG. 2 is an explanatory view showing the second embodiment of the present invention. In the figure, the control circuit generator of the present invention includes a data-dependent execution condition code generator 3a. In this case, the condition code is such as to indicate mutual exclusivity based on the data dependency.

When a certain operation result is not used in all leaf conditions of the conditional branch following it, and is not used thereafter, an operation for calculating the operation result and an operation executed under the condition not using the result Is exclusive. For example, the value of X in (1) of FIG. 4 is not used in the leaf condition of (6). That is, the execution of (1) and (6) is exclusive.

Such a data-dependent execution condition code gives the condition code described in the first embodiment to the operation node immediately before the branch end node of the control data flow graph, and the other nodes (nodes immediately after it) ( The condition code is obtained by the logical sum of the condition codes of the immediately following node). For example, (2) and (5) in FIG. 4 are nodes immediately before the branch end node, and the condition codes [100] and [001] are added according to the first embodiment. Since the nodes immediately after (1) are (2) and (5), the condition code of (1) is [101]. At this time, the condition codes of (1) in FIG. 4 (operation 1 in FIG. 6) and (6) in FIG. 4 (operation 4 in FIG. 6) are [101] and [010], which are the above-mentioned data dependency relationships. It shows mutual exclusivity based on. The condition code according to the second embodiment is shown in FIG.

FIG. 3 is an explanatory view showing a third embodiment of the present invention. In the figure, the control circuit generator of the present invention includes a dynamic execution condition code generator 3b. In this case, the condition code is such that it exhibits dynamic mutual exclusivity.

The dynamic mutual exclusivity is the mutual exclusivity that dynamically changes depending on whether or not the branch test of the conditional branch has been executed. For example, it is assumed that the operation step of the calculation of the control data flow graph of FIG. 6 is determined as shown in FIG. Then, when the operations 4 and 5 are executed, the execution of the conditional operation 7 is not completed. Therefore, since it is not possible to determine which of the operation 4 and the operation 5 should be executed in the operation step S2, both operations must be executed, and these two operations are not mutually exclusive, and the operation unit cannot be shared.

As described above, the exclusivity between operations dynamically changes depending on whether the conditional operation is completed before the execution of a certain operation. Such a dynamic execution condition code is obtained by taking the logical sum of the condition code of the conditional operation whose execution has not ended and the condition code of the operation for which the condition code is desired.
However, here, the branch condition operation is limited to the branch test operation that controls the execution of the target operation. That is, unless the condition code of the operation for which the conditional operation is desired and the condition code of the conditional operation have "1" at the same position, they are irrelevant to each other and do not perform a logical sum with such conditional operation.

FIG. 7 shows the condition codes when the above operation steps are given. Also, (u) and (e) in FIG.
Shows the condition code when the conditional operations (2) and (5) are not executed and when they are executed.

Next, the scheduling device 4 schedules the operation node of the control data flow graph having the condition code assigned to each operation as described above. Each operation node is parallelized so as to satisfy the data dependency relationship. An example of the result of such scheduling is shown in (1) of FIG.

The scheduling result is input to the control sequence generator 5. The control sequence generation device 5
The vector sum of the condition codes of all operations assigned to each step is taken. SALL in (2) of FIG. 8 indicates the vector sum of the condition codes of the operations in each step of the scheduling result in (1) of FIG. Here, “0” of the component of the vector sum of SALL (2) is searched for.

Since "0" in the vector sum indicates that no operation is executed under the condition of the bit position, this 0
Under the bit condition, the operation step may be skipped without executing. Therefore, when the control sequences are combined so as to jump over the 0 component by looking at the vector sum (2), the result becomes (4) in FIG. In the example in the figure, it is always 4
Depending on the conditions, the operation steps that have taken steps can be executed in four steps, two steps, or three steps, and the operation can be completed with an average small number of steps.

[0033]

According to the present invention, when a compiler or automatic function design is performed, it is determined whether or not an operation node or a storage element node can share the same operation unit or register without analyzing the structure of the control data flow graph. However, it is possible to provide a device that performs scheduling using the result and generates an efficient control sequence for the scheduling result.

Further, since it is possible to obtain a wider mutual exclusivity than the explicitly indicated mutual exclusivity, it is possible that more operations can share the same arithmetic unit, and the compiler outputs Quality (speed, area, memory capacity) of the synthetic circuit synthesized by machine language and automatic functional design
Can be improved. Even in such a case, it is possible to generate an efficient control sequence.

Since dynamic mutual exclusivity is required, the same operation is performed when the operation in the conditional branch is executed before the operation for testing the conditional branch when used for the compiler or automatic functional design. Can be determined whether it can be shared. By enabling such a design, the performance of the compiler and the automatic functional design system is improved. Even when such exclusivity between operations dynamically changes, an efficient control sequence can be generated.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a third embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of a behavioral description and its condition code.

5 is an explanatory view showing a branch structure of FIG.

FIG. 6 is an explanatory diagram showing an example of a condition code obtained by the second embodiment.

FIG. 7 is an explanatory diagram showing an example of a condition code obtained by the third embodiment.

FIG. 8 is an explanatory diagram showing an operation example of a control sequence generation device.

[Explanation of symbols]

 1 Control Data Flow Graph 2 Control Data Flow Graph Reading Device 3 Execution Condition Code Generation Device 4 Scheduling Device 5 Control Sequence Generation Device

Claims (3)

[Claims] 1. A device for generating a control circuit as a result of scheduling a control data flow graph, the control data flow graph representing a control of the operation of a circuit and a data flow, the control data flow graph reading device comprising: A control sequence for synthesizing an execution condition code generation device that receives the read control data flow graph, a scheduling device that performs scheduling by using the output of the execution condition code generation device, and a control device that controls the scheduled result. A control circuit generation device comprising: a generation device. 2. A data-dependent execution condition code generator for deriving the exclusivity between operations not explicitly shown in the control data flow grab from the data dependency relationship and for generating the operation execution condition code indicating the exclusivity between the operations. The control circuit generation device according to claim 1, wherein 3. A dynamic execution condition code generation device for generating an operation execution condition code that indicates the exclusivity of an intra-branch operation that dynamically changes depending on whether or not a condition determination operation for determining a branch of a conditional branch is completed. The control circuit generation device according to claim 1 or 2, further comprising: