JPS63198130A - System for selecting loop optimum instruction train - Google Patents

System for selecting loop optimum instruction train

Info

Publication number
JPS63198130A
JPS63198130A JP3096587A JP3096587A JPS63198130A JP S63198130 A JPS63198130 A JP S63198130A JP 3096587 A JP3096587 A JP 3096587A JP 3096587 A JP3096587 A JP 3096587A JP S63198130 A JPS63198130 A JP S63198130A
Authority
JP
Japan
Prior art keywords
loop length
instruction
train
generating means
cross
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3096587A
Inventor
Shoichi Sakon
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP3096587A priority Critical patent/JPS63198130A/en
Publication of JPS63198130A publication Critical patent/JPS63198130A/en
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To generate an object program which automatically selects the instruction train whose executing time is shorter between a scalar instruction train and a vector instruction train at the time of execution by providing a cross loop length calculation means, a comparison instruction generating means and a branch instruction group generating means in a compiler.
CONSTITUTION: A vector instruction train generating means 21 generates the vector instruction train for the loop in a source program and a scalar instruction train generating means 22 generates the scalar instruction train for the loop, then the cross loop length calculation means 23 obtains the cross loop length of the loop in the source program. The comparison instruction generating means 24 generates the comparison instruction for comparing the cross loop length calculated by the cross loop length calculation means 23 when the loop length is unknown at the time of compiling and it is known only at the time of execution, with the loop length at the time of execution and the branch instruction group generating means 25 executes the vector instruction train when the loop length is longer than the cross loop length calculated by the cross loop length calculation means 23 and generates the branch instruction for executing the scalar instruction train when the loop length is shorter than the calculated cross loop length based on compared result.
COPYRIGHT: (C)1988,JPO&Japio
JP3096587A 1987-02-13 1987-02-13 System for selecting loop optimum instruction train Granted JPS63198130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3096587A JPS63198130A (en) 1987-02-13 1987-02-13 System for selecting loop optimum instruction train

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3096587A JPS63198130A (en) 1987-02-13 1987-02-13 System for selecting loop optimum instruction train

Publications (1)

Publication Number Publication Date
JPS63198130A true JPS63198130A (en) 1988-08-16

Family

ID=12318384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3096587A Granted JPS63198130A (en) 1987-02-13 1987-02-13 System for selecting loop optimum instruction train

Country Status (1)

Country Link
JP (1) JPS63198130A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736709A (en) * 1993-07-20 1995-02-07 Nec Corp Procedure calling system
JP2009211458A (en) * 2008-03-05 2009-09-17 Nec Corp Compiler, variable-optimizing device, method, and program
JP2013175218A (en) * 2006-08-18 2013-09-05 Qualcomm Inc System and method of processing data using scalar/vector instructions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285544A (en) * 1985-06-12 1986-12-16 Hitachi Ltd Program executing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285544A (en) * 1985-06-12 1986-12-16 Hitachi Ltd Program executing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736709A (en) * 1993-07-20 1995-02-07 Nec Corp Procedure calling system
JP2013175218A (en) * 2006-08-18 2013-09-05 Qualcomm Inc System and method of processing data using scalar/vector instructions
JP2009211458A (en) * 2008-03-05 2009-09-17 Nec Corp Compiler, variable-optimizing device, method, and program

Similar Documents

Publication Publication Date Title
JPH0380337A (en) Parallel form producing device
JPH0493894A (en) Method and device for character processing
JPS5533280A (en) Data processing system
JPH02264329A (en) Automatic program generating device
JPH0242569A (en) Contex switching method and its device used for vector processing system
JPH0437927A (en) Processor processing method
JPH04215132A (en) Compiler optimizing method
EP0938044A3 (en) Methods and apparatus for reducing interference in a branch history table of a microprocessor
EP0899656A3 (en) Program conversion apparatus for constant reconstructing VLIW processor
JPH01121938A (en) Object generating system
JPS62159274A (en) Conversion system into vector by division and copy of conditional branch
JPS63132338A (en) Code generating method
JPH02300852A (en) Serialization control system for instruction execution
JPH03116234A (en) Multi-processor system having plural instruction source
JPH0498323A (en) Parallel execution system for process
JPS62226232A (en) Control system for branch instruction
JPH04215133A (en) Code optimizing method and compiler system
JPH0394303A (en) Timing generator
EP0790555A3 (en) Compile apparatus and method
JPH0362202A (en) Control program developing device
JPH0477823A (en) Processor
BECKMANN et al. The effect of barrier synchronization and scheduling overhead on parallel loops
JPS533753A (en) Microprogram brance-reset condition assigning system
JPH02183339A (en) Computer program converting apparatus and method
JPH0454636A (en) Processor