JPS58186848A - Data flow processing system - Google Patents

Abstract

PURPOSE:To handle a complicate application having high parallism, by executing processing independently at respective processing elements, and utilizing the parallelism of programs sufficiently, and performing instruction-level parallel execution efficiently. CONSTITUTION:A data flow processor 1 consists of plural processing elements 2 and a coupling network 3, and each processing element 2 is provided with an instruction controller 20 which inputs data and a token and an arithmetic device 23 which performs processing. Further, an operand memory 21 and a code memory 22 for storing an operand and a code allotted to the controller 20 of each processing element 2 are connected. Then, each processing element 2 performs procession allotted on the basis of the data and token inputted to the controller 20 independently and the coupling network 3 performs execution results among the respective processing elements 2. Thus, the respective processing elements 2 perform the procession to perform the instruction-level parallel processing efficiently, handling a complicate application with high parallelism.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data flow processing method that efficiently implements instruction-level parallel processing.

In conventional data flow processing devices, when assigning a program to a processing element in the processing device, there is a method of assigning a procedure, which is a processing unit of the program, to one processing element, and a method of assigning each processing element of an instruction when assigning a procedure to a processing element. A method of simply interleaving the assignment to each processing element using instruction addresses, and a method of randomly assigning instructions to each processing element have been used. However, with the former method, it is difficult to simultaneously process each instruction within a procedure, and with the latter two methods, there is a problem that the load is temporarily concentrated on a specific processing element, which may reduce performance. Ta.

The purpose of the present invention is to solve these drawbacks by allocating one of the destination instructions to which the execution result of the instruction is sent to the processing element in which the instruction is stored, and assigning the other destination instructions to the processing element in which the execution result of the instruction is stored. When there are destination instructions, instruction addresses are determined and executed so that they are assigned to different processing elements as much as possible, thereby efficiently realizing parallel execution at the instruction level. explain.

FIG. 1 shows a block diagram of a data flow processing device according to a first embodiment of the present invention, in which 1 is a data flow processing device, 2 is a plurality of processing elements (Processin
gElement), 3 is a connection network that interconnects a plurality of processing elements 2. In the figure, each processing element 2 in a data flow processing device 1 communicates with each other via a connection network 3 (for example, a connection network configured with multi-stage switches) in which the average data transfer time between two different processing elements 2 is equal. It is connected to the.

FIG. 2 shows a block diagram of the configuration of the processing element 2, in which 20 is an instruction control device, 21 is an operand memory that temporarily stores the data in the arrived token, and 22 is a controller in which the instruction code to be executed is stored. , - memory, and 23 are arithmetic units. Further, when a token carrying data arrives from the sticky network 3, the instruction control device 20 can execute all the operands necessary for executing the instruction based on the destination information indicating the instruction address of the token. and a function to temporarily store the data in the arrived token in the operand memo +) 21 if it is not executable.
When the instruction code is executable, it reads the instruction code from the code memory 22 in which the instruction code is stored, aligns the operand part according to the arrived token and the contents of the operand memory 2, and passes it to the arithmetic unit 23. The arithmetic unit 23 then performs arithmetic processing indicated by the instruction code on the data in the operand portion, and returns the result of the arithmetic operation to the connection network 3.

Next, the operation of the data flow processing apparatus in this embodiment will be explained using FIGS. 1, 2, and 3. The dataflow processing device operates by storing dataflow zolograms and executing the programs. Generally, a data flow graph is represented and created by a data flow graph as shown in FIG. In FIG. 3, codes 41, 42, 43, and 44 indicate instructions, and arcs (arrows) indicate data flows. For example x=a
*b-l-c *d value and y = a * b −
To explain the case of calculating the value of c * d (here, the mark * indicates a multiplication symbol) using Fig. 3, first input data a and b are given to instruction 4 (multiplication), and input data c,
d to instruction 42 (multiply). Instruction 4 and instruction 42 are each independently a*b,! : The value of X and y is calculated by performing the operation c*d, inputting each result to instruction 43 (addition) and instruction 44 (subtraction), and processing each independently. .

The assignment of each instruction and processing element in the above example will be explained next. Now, there are N processing elements 2 in the data flow processing device 1, each with 0. ■.

..., N-1 numbers are assigned.

In the above program example, for example, if instruction 4 is assigned to the first (0≦l≦N-1)7) processing element 2, then instructions 43 and 44, to which the execution result of instruction 4 will be sent, are assigned.
One of them, for example, the instruction 43, is assigned to the same processing element 2 as the processing element 2 to which the instruction 41 is assigned, and then the instruction 42 is assigned. The instruction 42 is assigned to the third (0≦iNj≦N-1) processing element 2 other than l in order to take advantage of the parallelism of the nologogram.

Of the instructions 43 and 44 to which the output of the instruction 42 is sent, the allocation of the instruction 43 has already been determined, so the remaining instruction 44 is assigned to the same processing element as the instruction 42.
, that is, it is assigned to the first processing element 2. This completes the allocation of processing elements corresponding to each process in the above example, and in FIG. 3, each portion surrounded by a dotted line indicates each allocated processing element. The source program coded from the data flow graph as explained above is processed by an assembler or computer programmer to determine the assignment of each instruction to a processing element, and after the assignment is completed, the program for each processing element is handled. By storing the code in the code memory 22 of the processing element 2, the SIBTA flow processing device becomes executable. That is, the second
If the processing element 2 shown in the figure is the 111th processing element, the instruction code of the code memory 22 instruction 4 and instruction 43 (6) will be stored, and the token that meets the data a from the connection network 3 will be stored. When the token carrying data b arrives at the command-based side [device 2θ, the processing element 2 starts arithmetic processing.

As shown in FIG. 4, the token carrying data a includes an operand section 3) (indicating data), a destination information section 33 indicating the storage address in the code memory 22 of the instruction code to process the data of the operand 3, and It is composed of a data modification part 32 (for example, in the case of a multiplication instruction, it indicates the distinction between a multiplier and a multiplicand) shown in operand 3, and the token carrying data b also has the same structure. When both data a and b become executable, the instruction control device 20
takes out the instruction code corresponding to instruction 4 from the code memory 22, collects the information necessary for a*b arithmetic processing, and sends it to the arithmetic unit 23. The arithmetic unit 23 performs a*b calculation, and the result is ? Return 3 mm braids. (In the above case, the data that arrives first is temporarily stored in the operand memory 2 until the next data arrives) Next, the processing element 2
3 will be executed, but in order to do so, the a that was just calculated
The result of *b and the result of C*d, which is separately and independently calculated by the other j-th processing element 2, are required as data. Therefore, in the same way, the command control device 20 of FIG.
The tokens carrying the results of *d will arrive separately. The token that arrives first is temporarily stored in the operand memory 2 until the last token arrives. Then, when all the data is collected, the information necessary for the computation is collected and passed to the computation device 23, where the computation process is performed. And the result is X. The third processing element also performs the same processing as above to calculate the value y.

As explained above, in the first embodiment, when operating the data flow processing device, the data dependencies between each instruction in the data flow program are used as a guide to control the assignment to the processing elements of the program. A program library is statically determined at the time of installation or assembling, and is stored in a program library that corresponds to each processing element.Since each processing element is executed independently according to the data flow, the parallelism inherent in the program is reduced. This has the advantage that the characteristics can be efficiently utilized in the data flow processing device.

FIG. 5 shows the configuration of a data flow processing device according to a second embodiment of the present invention. In the figure, l is a data flow processing device, 2 is a processing element, and 5 is a connection network in which a local topology is introduced into the connection between each processing element 2 (for example, a connection network in the form of a network using a ring bus). The processing elements 2 are connected in network form by a coupling network 5.

Furthermore, the configuration of the processing element 2 is the same as that shown in FIG.

In such a configuration, in order to take advantage of the locality of communication between each processing element 2, the assignment of each instruction to the processing element 2 requires a little more effort than in the first embodiment.

That is, although the combined network 3 in the first embodiment had the same average data transfer time between different processing elements 2, in the case of the present example, the combined network 5 has a network configuration. This means that the data transfer speed between each processing element is different. Now, data flow processing device J
There are N1h processing elements 2 within, 0, 1, 2 respectively.
．． . . , N-1 (9) It is assumed that numbers are assigned in the trench, and each of these processing elements 2 is connected by a ring bus through the connection network 5. (However, it is assumed that the N-1il-th processing element 2 is connected to the O-th processing element 2.) When applying the Glodarum example shown in FIG. 3 in this embodiment,
Assuming that instructions 4 and 43 are assigned to the first processing element (0≦i≦N-1), instructions 42 and 44 select a value different from l that is closest to i, and perform the j-th processing. Elements need to be assigned. That is, by allocating in this way, the transfer time is shortened, and the overall processing time can be shortened. In this case, the relationship between l, j, and N is j = mod (i+1 p N) or j = m
od (i-1# N) (here mod (x, y
) indicates the remainder when X is divided by y). In this embodiment as well, during assembly or assembly, the assignment of each instruction to a processing element is determined using the above method, and the program corresponding to each processing element is stored as in the first embodiment. Then, each processing element is executed independently according to the data flow (10). Therefore, the second embodiment also has the advantage that the parallelism inherent in the program can be efficiently utilized in the data flow processing device.

The invention is to statically allocate each instruction in a program to a processing element in advance using data dependencies as clues, and store the program corresponding to each processing element.
Since the arithmetic processing in each processing element is executed independently, it is possible to take full advantage of the parallelism of the program, and it can be used for complex applications with a high degree of parallelism, such as numerical calculations and inference functions in knowledge information processing. - It can be used in a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data flow processing device in the first embodiment of the present invention, FIG. 2 is a configuration diagram of processing elements, FIG. 3 is an explanatory diagram showing an example of a data flow graph, and FIG. 4 is a token diagram. FIG. 5 is a configuration diagram of a data flow processing device in a second embodiment of the present invention. l...Data flow processing devices 1, 2...Processing elements,
3.5...Connection network, 20...Command control device, 2-
... Operand memory, 22 ... Code memory, 23
...Scaling device, 3....Token operand part,
32... Token operand modification part, 33... Token destination information part, 41, 42, 43.44... Instruction. Figure 1 Figure 2 ■--- Figure 3 Figure 4 Figure 5 Figure 2

Claims (1)

[Claims] It has an instruction code storage unit that stores multiple instructions, an instruction code storage unit that temporarily stores arriving data, an arithmetic unit that executes specified instructions, and all the data necessary for the operation. and an instruction control device having a function of detecting whether or not the instruction code stored in the instruction code storage section and the y''-data necessary for the operation are ready for execution and sending them to the arithmetic unit. A plurality of processing units to be processed are connected by a connection network having a data reception and transmission function, and one of the destination instructions to which the execution result of the instruction in each processing element is to be transferred is connected to the destination instruction when the instruction is executed. storing an instruction program for each processing element obtained by assigning the instruction to the processing element and assigning another destination instruction to a mutually different processing element other than the processing element, corresponding to the instruction code storage section of each processing element; A data flow processing method characterized in that each of the processing elements is executed independently according to the flow of data.