JPH0448370A - Interruption processing method for executing arithmetic operation in cascade fashion - Google Patents

Abstract

PURPOSE:To eliminate the waste time of a reception processor by performing an arithmetic operation in cascade fashion by executing prescribed first processing when a checked result shows a specific value ad executing prescribed second processing when it shows a value other than that. CONSTITUTION:Each of element processors (PE) 1-4 executes a cascade calculation execution instruction by executing processing 1, and takes synchronization for the whole by executing processing 2. The PE1 and PE3 perform transmission processing to the PE2 and PE4 immediately after executing the cascade calculation execution instruction, and perform the processing 2. The PE2 executes the processing 2 after executing the cascade calculation execution instruction, and executes the transmission processing to the PE4 on the extension of interruption processing when receiving an addition request from the PE1 during that time, and returns to the execution of the processing 2. thereby, since a transmission operation can be executed as the extension of a reception operation at a time when it is requested, the waste and idle time of the processor can be eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel computer in which a plurality of processing units are interconnected, and particularly to control when a parallel computer executes a cascade type operation such as summation calculation. Suitable.

[Conventional technology]

In the following, local memory refers to a storage device contained within a processing device. Each processing unit can directly access its own local memory, but cannot directly access the local memory owned by other processing units.When a processing unit accesses local memory owned by another processing unit, A packet requesting access is sent to the other processing device, and the other processing device writes data, reads data, and sends the data. As a computer with such local memory, "Parallel Computer Construction Theory J (January 1986, Shokodo edition, written by Shinji Tomita), pages 102 to 10
Parallel computer system rILLIA described on page 4
There is CIVJ.

Mutual coupling networks that couple processing devices to each other include path coupling networks, ring coupling networks, and lattice coupling networks.

There are binary tree connection networks, hypercube connection networks, crossbar connection networks, connection networks using multi-stage switches, etc. (see, for example, the above-mentioned ``Parallel Computer Configuration Theory'', pages 69 to 98).

Performing cascade-type operations means performing summation-type calculations (summation calculations, inner product calculations, maximum value calculations, minimum value calculations, etc.) on a parallel computer system in which multiple processing units with local memory are interconnected. It's a method. Regarding the total sum calculation, as described in Japanese Patent Application Laid-Open No. 1-147767, one partial sum of each 02 pieces of data is taken. ■Re-calculate the partial sums for each two pieces. By repeating the following (■), the summation can be obtained.

A parallel computer with a processing request function is published in Japanese Patent Application Laid-Open No. 1-13194.
9. Parallel computer with processing request function”. In a parallel computer in which a plurality of element processors, each having a memory for data retention, are connected through a network so that they can communicate with each other, a first element processor held in a first memory connected to the first element processor is used. data, an address specifying the second data in a second memory connected to the second element processor; Second
A processing request including the type of processing to be performed on the second data connected to the first element processor is sent from the first element processor to the second element processor. the second element processor provided in the second element processor in response to the address;
Read second data from the memory, perform processing on the first data and second data, and store the resultant data of the processing in the second memory.

[Problem to be solved by the invention]

Among the conventional techniques, the method described in Japanese Patent Application Laid-Open No. 1-147767 requires synchronization when transmitting and receiving information between two processing devices, which wastes time on the receiving processing device. This is because once the receiving-side processing device executes the receiving command, it continues to wait until it receives the data.

On the other hand, in a parallel computer with a processing request function described in JP-A-1-131949, the processing unit on the sending side selects the local memory address (of the processing unit on the receiving side) where the data is located, the data to be added, and the processing to be performed. A processing request including the type (addition) is sent to the receiving processing device. Upon receiving this processing request, the receiving side processing device interrupts the process being executed and compares the data specified in the received processing request between the data in the received processing request and the data at the local memory address in the received processing request. The processing to be performed (addition) is executed and the result is stored in the local memory address in the received processing request.

Therefore, in a parallel computer having a processing request function, the time of the processing device on the receiving side is not wasted by executing the receiving command.

However, even on a parallel computer with a processing request function, sum calculation (
Another problem arises with cascade calculations. That is, the processing device that received the processing request needs to send the added result this time (with the exception of the processing device that obtains the last result because it does not send it). To submit your problem,
The point is that it must be confirmed that the processing request has been received and the addition has been completed. This causes a wait for confirmation.

In order to avoid waiting during confirmation, it is sufficient that the sending of the processing request at the sending side processing device is performed at a time interval before the confirmation at the receiving side processing device. As shown in the figure, in cascaded computation, confirmation is a pre-operation to sending, and delaying the confirmation point will delay sending, which will delay the confirmation of the next receiving processing device.

In FIG. 11, each processing device (hereinafter abbreviated as PE: element processor) executes process 1, performs summation calculation, and then executes process 2. After executing process 1, PE1 and PE3 check whether the addition request has been received and processed from another PE. Since there is no PE requesting processing for PEI and PE3, they immediately execute transmission processing to PE2 and PE4, respectively, and then execute processing 2. On the other hand, PE2
Then, after confirming the reception and processing of the addition request from the PEI, the transmission processing to PE4 is executed, and then processing 2 is executed. PE4 executes process 2 after confirming the reception and processing of the addition requests from PE3 and PE2. The final overall synchronization is synchronization for making all PEs take the same step.

Therefore, even if there is sufficient time from the start of a cascade-type calculation to the reference to the result of the calculation, there is idle time in the processing device, that is, wasted time. In FIG. 11, there is idle time for waiting for confirmation and waiting for overall synchronization.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cascade type calculation execution method that can eliminate the wasted time of a processing device for reception if there is enough time from the start of the cascade type calculation to the reference of the result.

[Means for Solving the Problems] In order to achieve the above object, in the present invention, a processing device that receives data combines the received data with data at a first predetermined location in a storage device held by the processing device. After executing a predetermined first operation (operation executed in a cascade type operation) between A predetermined second operation is performed on the data at a second predetermined location in the storage device held by the processing device, and if the result of the second calculation is 0, the data at the first location in the storage device held by the processing device is executed. The process returns to the process before transmitting the data of the predetermined location to another processing device and receiving the data, and if the second calculation result is not 0, nothing is done and the process returns to the process before receiving the data.

[Effect]

The processing device that has received the data subtracts 1 from the counting counter (data at the second predetermined location) (second calculation) to check whether all the information to be received has been received. When the counting counter becomes O, all the information has been received, so if the processing device itself is not the root processing device (from which the final result can be obtained), the data at the first predetermined location in the storage device owned by the processing device is to another suitable processing device. If the device itself is a root processing device, it notifies the end of cascade calculation. In the present invention, the transmitting operation is performed as an extension of the receiving operation when it becomes necessary, so there is no wasted idle time of the processing device.

FIG. 12 is a diagram showing the waiting time of PE according to the present invention. In FIG. 12, each PE executes process 1, executes a cascade calculation execution command, and executes process 2 to achieve overall synchronization. After executing the cascade calculation execution command, PEl and PE3 immediately perform transmission processing to PE2 and PE4, respectively, and execute processing 2. After executing the cascade calculation execution command, PE2 executes process 2, and if it receives an addition request from PEI during that time, it executes a transmission process to PE4 as an extension of the interrupt process, and returns to process 2. After executing the cascade calculation execution command, PE4 executes process 2, and during that time receives addition requests from PE2 and PE3. When received for the second time, the end of cascade calculation is notified.

〔Example〕

Example 1: An example of the present invention will be described with reference to the drawings. First, an information processing apparatus according to the present invention will be explained.

FIG. 2 is an explanatory diagram of one element processor.

The element processors 1 are coupled to other element processors (not shown) via a connection network control circuit 3.

FIG. 3 is an overall diagram of a computer system in which a plurality of element processors are interconnected. In FIG. 3, 2 is a connection network between element processors, and 4 is a host computer that controls the entire system. 6 In this embodiment, the connection network is a hypercube (as described above).
It is assumed that the topology includes the topology of "Parallel Computer Configuration Theory", pages 79 to 80).

The element processor 1 is basically a von Neumann type computer, and also has the function of communicating with other element processors 1 via the interconnection network control device 3.It also has the function of communicating with other element processors 1 through the connection network control device 3. contains some instructions for implementing the present invention, which will be described in detail later. In FIG. 2, for the sake of simplicity, parts of the functions of the von Neumann computer that are not related to the present invention are omitted.

In FIG. 2, 5 is a reception flag and 7 is a reception register.

Is the connection network control circuit 3 the receiving register 7? After writing this information, the control circuit 9 turns on the reception flag 5, and when the processing of the information in the reception register 7 is completed, the control circuit 9 turns on the reception flag 5. f
Make it f. 13 is the own PE# register and the value of the unique number assigned to this element processor 1 is written 0.
In this embodiment, the address of each element processor on the hypercube is used as the element processor number. 1
A program counter 5 stores an address (in the storage device 17) where the next instruction to be executed is stored.

19 is a transmission register, and 21 is a transmission flag.

When the control circuit 9 writes information to the transmission register 19, it sets the transmission flag 21. n, and the network control circuit 3 transfers the information in the transmission register 19 to the network control circuit 3 coupled to another element processor 1, and then turns off the transmission flag 21. 9 is a control circuit for the element processor 1, which is the main part of the von Neumann type computer. 11 is a general-purpose register of the von Neumann type computer.

23 is a receiving buffer inside the network control circuit 3. A receiving buffer is provided corresponding to the network control circuit 3 connected to the network control circuit 3 through a line. (For example, if this network control circuit is connected to 7 network control circuits by a line, it will have 7 reception buffers.) Figure 4 shows the data stored in the reception register 7, transmission register 19, and reception buffer 23. It is an explanatory diagram of a format of information (hereinafter referred to as a packet). 401 in FIG. 4(a) is the format of information (hereinafter referred to as an output packet) stored in the reception register 19 and reception buffer 23. The output packet 401 is basically divided into four fields. 4o3 is a destination PE number field, which contains the number of the element processor that should receive this packet.

405 contains the length (bit length) of the data field 409 of this packet, and the processing code field 407 indicates the type of processing to be performed on this packet. These three fields (403, 405, 407) are fixed. It is long. 4o9 is a data field, and the length of this field varies depending on the processing code 407. 40 again
The data field 9 is divided into several subfields depending on the value of the processing code 407. Here, subfields of a cascade calculation processing request packet according to the present invention are shown. 411 contains the address of a cascade control block (hereinafter abbreviated as CCB), which will be described later, and 413 contains target data for cascade calculation.

Next, 402 in FIG. 4(b) is the format of information stored in the reception buffer 7 (hereinafter referred to as a reception packet).
The received packet 402 is sent from the transmitted packet 401 to the destination PE.
This excludes the number field. 406 is a data length field, 40g is a processing code field, 410
is a data field. The explanation of these contents is the same as that of the transmission packet, so the explanation thereof will be omitted.

When the connected network control circuit 3 writes information to the reception register 7, the destination PE number field 403 is removed. 25 is a register for loading the contents of ccB, which will be described later;
7 is a register for loading the operand subfield 413 in the received packet 402 according to the present invention;
9 is a register into which the CCB address is loaded.

Functions of Network Control Circuit> As shown in FIG. 3, the element processors are connected to other element processors via the network control circuit 3. The connection network control circuit 3 has the following functions.

(1) A transmission packet 401 as shown in FIG. 4 is received from the connection network control circuit of another element processor and stored in the reception buffer 23.

(2) If the destination PE number field 403 of the transmitted packet is different from the number added to the element processor 1 to which it is connected, the packet is transferred to the connected network control circuit 3 connected to the appropriate element processor 1 do.

(3) When the destination PE number field 403 of the transmitted packet matches the number added to the element processor 1 to which it is connected, wait for the reception flag 5 of the connected element processor 1 to turn off. 405, 407, and 409 obtained by removing the destination PE number field 403 from the transmission packet 401 are written in the reception register 7, and a reception flag is set. Make it n.

(4) The transmission flag 5 of the element processor 1 to which it is connected. When n is reached, the transmission packet 401 in the transmission register 19 is transferred to the destination PE number field 4 of that packet.
The data is transferred to an appropriate network control circuit 3 so that it reaches the network control circuit 3 connected to the element processor 1 specified by 03.

<Cascade Control Block> In implementing the present invention, data having a structure called a cascade control block (CCB) is used to control cascade-type execution of operations. In this embodiment, this is configured on the storage device 17 of the element processor 1. Let me explain its composition.

The CCB consists of the following six fields as shown in FIG.

(a) Address 201 of the variable containing the result of cascade calculation (b) Interrupt counter 203 (c) CC
Field 205(d) representing the status and attributes of B, Loop PE number 207(e) Address 209(f) of program a, Address 211 of program b and above fields will be briefly explained.

(a) is self-explanatory; (b) contains the number of element processors 1 that have this element processor as a parent. (c) will be processed later. (d) contains the number of element processor 1 that obtains the final result of the cascade calculation. In (e), the address of program a that sends a transmission packet from this element processor 1 to the parent of this element processor 1 is entered. (f) is a program b that notifies that the cascade calculation has finished.
The address is entered.

Furthermore, the attribute field 205 in (c) includes at least the following elements.

(cl) Cascade calculation type 213 (C2) Interrupt permission flag 215 Cascade calculations include summation calculation, maximum value calculation, minimum value calculation, etc. These are distinguished by a value of 213. 21
5 is a flag that gives permission to start the program 209. This is set when a cascade calculation instruction (described later) is executed in this element processor 1.

Below, it will be described how the present invention is realized under the circuit configuration described above. First, the format of the cascade calculation execution command will be described.

The execution command for cascade calculation has the following format.

■ CASCR1, L2 ■ CASCRR1, R2 Here, R1 specifies a register (general-purpose register or floating point register) that holds data to be subjected to cascade calculation. In format 2, L2 specifies the CCB address on the storage device represented by pace register + index register + offset. In format 2, R2 specifies a general-purpose register containing the address of the CCB.

Operation upon Execution of Cascade Calculation Instruction> The operation upon execution of the cascade calculation instruction will be described with reference to the flowchart in FIG. Here, explanation will be given according to the format (■).

(1) Calculate the CCB address of label L2, and
It is stored in the address register 29, and variable address 201. Counter 203, attribute field 205. Root PE number 207. Address 209 of program a. Load address 211 of program b into CCB register 25. (601) (2) Perform the specified calculation in 213 between the contents of R1 and 200 and store the result in 200.

(3) If the count counter 203 is other than O, store 203 in the original CCB and end the process. (605) (4) When the counting counter 203 is 0, the root PE number 207 and the contents of the own PE number register 13 are compared. (607) (5) If the results of the comparison match, the program 219 is called, the end of the cascade calculation is notified, the counting counter 203 is stored in the original CCB, and the process ends. (609) (6) If the results of the comparison do not match, call the program 217, send it to the parent element processor 1, store the counting counter 203 in the original CCB, and end. (61
1) Next, the transmission process 217 to the parent PE will be explained.

(1) Calculate the destination PE number from the own PE# register 13 and the root PE number 207 in the CCB.

In this embodiment, the parent PE number is obtained by comparing 13 and 207 starting from the lowest hit, and inverting the bit of 13 at the bit position where the first non-matching bit exists.

(2) The transmission flag 21 is set. Wait until it becomes ff.

(3) Create a transmission packet 401 in the transmission register 19. The value calculated in (1) above is written in the destination PE number field 403, and the data length field 405 and processing code field 407 transfer the values of the CCB register as they are. The contents of the CCB address register 29 are transferred to the address subfield 411 of the data field 409, and a value of 200 is written to the operand subfield.

(4) Turn on the transmission flag and end the transmission process.

Third, the cascade type calculation end notification process 219 will be explained. This process notifies the program of the end of the cascade calculation, and normally uses a system macro.In this embodiment, synchronization is achieved using a macro called post. That is, those who wait for the completion of the cascade calculation use a macro called wait, and those who notify the completion use a macro called post. For details, see "Practical Operating System J (March 1980, Shokodo edition, written by Yasufumi Yoshizawa) 143.
See pages 144 to 144.

Processing when a cascade calculation processing packet of the present invention is received will be explained with reference to FIG.

The control circuit 9 checks the reception flag 5 every time one command is completed. When the reception flag 5 is on, the processing code field 408 is entered, and when it is a code for cascade calculation processing, the process moves on to the following processing. The processing for other codes will also be repeated, but since they are irrelevant to the present invention, they will be omitted here.

(1) Load the address subfield 411 in the received packet 402 into the CCB address register 29, and select the variable address 201. from the CCB indicated by the address subfield. Count counter 203, attribute field 205.
Root PE number 207, program a address 209.
Load address 211 of program b into CCB register 25. <101) (2) Load operand subfield 413 in received packet 402 into data register 27. (103
(3) Perform the calculation specified in the calculation identification field 213 between the contents of the data register and the contents of the 200 variables specified in the CCB, and store the result in the 200 variables. (
10B) (4) Subtract 1 from the counting counter 203.

(5) If the count counter 203 is not 0, the process ends.

(109) (6) If the interrupt permission flag 215 is off, the process ends. (111) (7) Compare the contents of the own PE# register 13 and the root PE number field 207 of the CCB. (113) (8) If the contents of the own PE# register 13 match the root PE number field 207 of the CCB, the CCB calls the designated program b219 and ends. (115) (9) If the content of the own PER register 13 and the root PE number field 207 of the CCB do not match, the CCB calls the designated program a217 and ends. (117) Embodiment 2: Next, as Embodiment 2, an example will be described in which the initial setting of the CCB is performed at the time of executing the first cascade calculation or receiving the cascade calculation.

As an example, only FIG. 1 is changed to FIG. 7, and FIG. 6 is changed to FIG. 8.

First, the operation when the CASC instruction is executed will be explained with reference to the flowchart of FIG. Format ■CA';C
The explanation will be based on the R format.

(1) Read the CCB from the address specified by the contents of R2 on the storage device 17 to the CCB register 25 and copy the contents of 5R2 to the CCB address 29.

(2) Perform the specified operation in 213 between the contents of R1 and the contents of 200 specified in CCB, and store the result in 200. (803) (3) Check the value of the counting counter 203, and if the value is positive, the process ends; if the value is negative, the process branches to (7).

(4) Root PE number field 207 in CCB and own P
The contents of the E# register 13 are compared.

(5) When 207 and 13 match, the designated cascade type calculation end notification process is called at address 211 of program b in the CCB, and the process ends.

(6) If 207 and 13 do not match, call the transmission process to the specified parent PE at address 209 of program a in the CCB, and end. (811) (7) Counter 20
In this example, the value to be set is the own PE#.
Exclusive OR is performed between the contents of the register 13 and the number field 207 of the root PH in the CCB, and this is the number of consecutive O's starting from the lower bit of the result. (813) (8) Check the value of the initialized counter, and if it is 0, branch to (5), and if it is not 0, end.

Next, the operation when a packet of cascade type calculation processing is received in the second embodiment will be explained based on the flowchart of FIG.

(1) Load the address subfield 412 in the received packet 402 into the CCB address register 29,
The CCB is loaded into the CCB register 25 from the address specified by . (701) (2) Load the data field 413 in the received packet 402 into the data register 22.

(3) Contents of data register 22 and 20 specified by CCB
A specified operation is performed in 2136 with the data of 0, and the result is stored in 200. (705) (4) If the count counter 203 is negative, the process branches to (6). (707) (5) Initialize the counting counter 203. (719
)(6) Subtract 1 from the count counter 203.

(7) If the count counter 203 is other than 0, the process ends.

(8) If the interrupt permission flag 215 is off, the process ends. (713) (9) Root PE number field 207 in CCB and own P
Compare with the contents of the E# register. (715) (10)
If the contents of 207 and 13 do not match, the transmission process to the designated parent PE is terminated at address 209 of program a of the CCB. (717) (11) If the contents of 13 and 207 match, program b specified by CCB
Call 219 and exit.

Effects of Example 2 The effects of Example 2 will be described here. In the structure of the CCB shown in FIG. 5, only the interrupt counter has a different value depending on the element processor. Values for other parts can be set when the program is loaded into a storage device or when compiled. When the number of element processors is large, it is impractical to load a different program to each element processor.In Example 2, if a negative value is set to the interrupt counter at compile time, the program is initialized at run time, which simplifies programming. do.

Embodiment 3: (In this embodiment, the second operation is a shift operation) In this embodiment, FIG. 1 is replaced with FIG. 9, and FIG.
Replaces figure 0. First, the operation when a cascade type calculation execution instruction is executed will be explained based on FIG. 10. Here, we will explain the case where an instruction of format (2) is executed.

(1) Calculate the address of label L2 and store it in the CCB address register 29, and load the contents of the CCB into the CCB register 25 from the address. (1001) (2) Perform the specified operation in 213 between the contents of R1 and the contents of variable 200 specified in CCB, and store the result in variable 200. (1003) (3) Counter 203
Check the least significant bit of , and if it is 0, branch to (7). (
1005) (4) Contents of own PE# register 13 and CCB
The PE number fields 207 of the roots in the middle are compared, and if they match, the process branches to (6). (1007) (5) If the contents of 207 and 13 do not match, the CCB calls the transmission process to the specified parent PE at address 209 of program a,
finish. (1011) (6) If the contents of 13 and 207 match, the specified program b219 is called in the CCB and the process ends.

(7) Set the interrupt permission flag 215 in the CCB and end. (1013) Next, the operation when a packet of cascade type calculation processing is received in the third embodiment will be explained based on the flowchart of FIG.

(1) Address subfield 412 in received packet
is copied to the CCB address register 29, and the contents of the CCB are loaded into the CCB register 25 from the address.

(901) (2) Load the data subfield 414 in the received packet into the data register 22. (903) (3) Perform the operation 213 between the contents of the data register and the data 200 specified by the CCB, and store the result in 200. (905) (4) Shift the counting counter 203 to the right by 1 bit.

(907) (5) If the least significant bit of the counting counter is O, the process ends. (909) (6) The interrupt permission flag 215 is set. If it is ff, the process ends. (911) (7) Compare the root PE number 207 in the CCB and the own PE# register 13. (913) (8) If the comparison results match, the designated 219 is called at address b of the CCB and the process ends.

(9) If the comparison results do not match, the designated 217 is called at address a of the CCB and the process ends.

Effects of Example 3 The effects of Example 3 will be described here. The feature of the third embodiment is that the initial setting of the counting counter is simple. Example 1
and 2, the initial value of the counting counter is the own PE# register 13.
and the root PE number field 207 in the CCB, which is the number of consecutive 0 bits starting from the least significant bit.

On the other hand, in the third embodiment, the initial value of the counting counter is
# This is the exclusive OR of the contents of the register 13 and the root PE number field 207 in the CCB.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the waiting time due to waiting for data arrival and the waiting time due to overall synchronization in cascade type calculation.

[Brief explanation of drawings]

FIG. 1 is a flowchart of the operation of an element processor when receiving a cascade calculation processing request packet according to the present invention, FIG. 2 is an explanatory diagram of one element processor, and FIG.
The figure is an explanatory diagram of the entire parallel computer system combining element processors, Fig. 4 is an explanatory diagram of transmitting packets and receiving packets, Fig. 5 is an explanatory diagram of the structure of CCB, and Fig. 6 is a cascade type calculation execution according to the present invention. A flowchart of the operation of the element processor when executing an instruction. FIGS. 7 and 8 are a flowchart of the operation of the element processor when receiving a cascade calculation processing request packet in the second embodiment, and a flowchart of the operation of the element processor when executing the cascade calculation execution instruction. 9 and 10 are flowcharts of the operation of the element processor when receiving a cascade calculation processing request packet in the third embodiment, and a flowchart of the operation of the element processor when receiving a cascade calculation execution instruction in the third embodiment. Operation flowchart, 11th
The figure is an explanatory diagram of a cascade type calculation performed by a parallel computer having a processing request function according to a conventional example, and FIG. 12 is an explanatory diagram of a cascade type calculation performed according to the present invention. ￥ 1 Diagram No. 1 Diagram Compilation ■ Tomizu Tomizu Country No. 1/ Diagram H1 EZ E3 EIL

Claims (1)

[Claims] 1. In a parallel computer having a processing request function, a first element processor in the parallel computer receives and executes first data and second data from a second element processor in the parallel computer. receiving as an interrupt a processing request including a type of processing to be performed; and data at a first address calculated from the first data and the second data in a storage device of the first element processor. executing a predetermined first operation between and storing the operation result in a first address calculated from the second data in a storage device of the first element processor; The data at the second address calculated from the second data in the storage device of one element processor is
executing the calculation and storing the calculation result in a second address calculated from the second data in a storage device of the first element processor; If the checked result is a specific value, a predetermined first process is executed, and if the checked result is not the specific value, a predetermined second process is executed. An interrupt processing method for executing an operation in a cascade type, characterized in that the step of executing the process executes the operation in a cascade type. 2. The method according to claim 1, wherein the first process includes the step of checking a flag bit at a third address calculated from the second data in a storage device of the first element processor; 1. An interrupt processing method for executing arithmetic operations in a cascade type, comprising the step of executing a predetermined third process when a flag bit has a predetermined value. 3. An interrupt processing method for executing operations in a cascade type in the method according to claim 1 or 2, wherein the second operation is addition or subtraction of a constant value. 4. A method according to claim 1 or 2, in which the second operation is a 1-bit shift operation, using interrupts to execute operations in a cascade type. 5. In the method according to claim 1 or 2, the second
for performing an operation in a cascade type, characterized in that when the result of the operation or the result of checking the result of the second operation is a specific value or a value in a specific range, an initial value is set at the second address. Interrupt handling method. 6. An interrupt processing method for executing an operation in a cascade type in the method according to claim 5, wherein the second operation is subtracting 1, and the specific range is negative.