JPH04102161A - Data processor - Google Patents

Abstract

PURPOSE:To shorten a period for testing operations by providing a selecting circuit to select one of outputs from a CPU and an external device and a buffer register to store the output of the selecting circuit in a vector unit. CONSTITUTION:An instruction and an operand are transmitted from an SVP 4 to a selecting circuit 6, and an SVP command is transmitted to an SVP command control circuit 7 so as to decode a P command. When the input to the selecting circuit 6 is the instruction and the operand, a control signal is transmitted for instructing the output of them to an instruction buffer 8 and an operand buffer 9. When the instruction and the operand are completely stored in the instruction buffer 8 and the operand buffer 9, they are transmitted from the SVP 4 to the SVP command control circuit 7 according to a command for activation, and the activation of executing the vector instruction is instructed from the SVP command control circuit 7 to a vector instruction transmission control circuit 10 so as to execute vector arithmetic. Then, a vector instruction control part 11 controls the condition of executing the vector arithmetic. Thus, the period for testing operations can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding a data processing device having a vector processing mechanism, the operation test of the entire data processing device can be performed by performing an operation test of the vector unit in parallel with an operation test of the CPU.
The purpose is to shorten the period, and the vector unit is C
It includes a selection circuit that selects one of the outputs of the PU and the external device, and a buffer register that stores the output of this selection circuit.

[Industrial application field]

The present invention relates to a data processing device.

[Prior Art] In recent data processing devices called supercomputers, in addition to the conventional CPU, new processors,
For example, a vector unit or the like is provided. In such a supercomputer, a CPU decodes an instruction and, if the instruction is a vector instruction, sends the instruction to the vector unit. At this time, if the operand of the vector instruction requires data in a general-purpose register or floating-point register within the CPU, that data is also sent to the vector unit.

Conventionally, in supercomputer operation tests, the vector unit operation test could only be performed after the CPU operation test was completed. This is because the operation of the vector instruction becomes possible only when the CPU reliably executes instruction fetching, decoding of the instruction, transfer of the instruction to the vector unit, etc., such as the vector instruction.

Therefore, since the vector unit is tested after the CPU has started operating, it takes a long time to test the entire supercomputer.

[Problem to be solved by the invention]

The present invention eliminates the drawbacks of the prior art described above and provides a data processing device that is capable of testing the operation of the vector unit in parallel with the CPU, and therefore shortens the total operation test period of the entire data processing system including the vector processing mechanism. The purpose is to

[Means to solve the problem]

A data processing device according to the present invention includes a first processor that processes a first type of instruction itself and transfers a second type of instruction to another, and a second type of instruction that is transferred from the first processor. a second processor that processes instructions; and an external device that supplies the second type of instructions to the second processor, the second processor selecting one of the outputs of the first processor and the external device. and a buffer register that stores the output of the selection circuit.

The data processing device according to the present invention is further configured such that the selection operation of the selection circuit can be controlled by a command from an external device.

[Effect]

In the operation test of the second processor, a command for setting the test mode is sent from the external device to the second processor. In the second processor, the selection circuit is switched to select the output of the external device. A second type of instruction for operation test is sent from the external device and sent to the buffer register via the selection circuit. Stored.

Predetermined processing is performed on the instructions stored in the buffer register.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a data processing device according to the present invention.

In FIG. 1, 1 is a normal CPU, and memory 2
reads instructions and data stored in the computer, decodes the instructions, and controls execution of the instructions. A portion 3 surrounded by a dotted line indicates a vector unit. When the instruction decoded by CPtJl is related to a vector operation, the vector unit 3 is a processor that is supplied with the instruction (including operands) from the CPU 1 and executes the vector operation.

A service processor (SVP) 4 is an independently operated external device, and in the present invention, selects the operating mode of the vector unit, supplies vector instructions during the test mode, and the like.

The vector unit 3 has a plurality of selection circuits 6, and the outputs of CPUI and 5VP4 are input to each selection circuit 6.

The SVP command control circuit 7 receives a command from the 5VP 4, decodes it, and sends a control signal to each selection circuit 6 based on the result. Each selection circuit 6 selects and outputs one of the two inputs from the CPUI and 5VP4 according to this control signal.

An instruction buffer 8 for storing vector instructions and an operant buffer 9 for storing scalar operands are connected to the output of each selection circuit 6, respectively.

When the selection circuit 6 selects the output of 5VP4, the selection circuit 6 selects the output of 5VP4.
The control signal from the SVP command control circuit 7 determines which of the instruction buffer 8 and operand buffer 9 the output data of No. 4 is to be stored in.

The outputs of each instruction buffer 8 and each operand buffer 9 are input to a vector instruction transmission control circuit 10. The vector instruction generation control circuit 10 transmits an instruction to the SVP command control circuit 7 from the 5VP4 when instructions and operands have been stored in all instruction buffers 8 and operand buffers 9, respectively, in response to a control signal from the SVP command control circuit 7. A command is given to activate the vector instructions stored in buffer 8 and operand buffer 9. This activates the vector instruction.

Instructions and operands are sent to each arithmetic pipeline of vector arithmetic unit 12 for processing.

The vector instruction management unit 11 manages the arithmetic processing and notifies the 5VP 4 of the completion of the arithmetic operation via the SVP command control circuit 7.

Note that the memory access control unit 5 controls access to the memory 2 since the vector unit 3 functions as a processor.

The operation of the circuit shown in FIG. 1 will be explained below.

In the operation test of vector unit 3, first 5VP4
sends an SVP command for setting the test mode to the SvP command control circuit 7. The SVP command control circuit 7 decodes the SVP command, learns that it is in the test mode, and sends a control signal to each selection circuit 6 to select the output of 5VP4 from the two outputs of CPUI and 5VP4. All selection circuit 6 is 5VP
Preparations for inputting the test data from step 4 are completed.

An instruction and an operand are sent from the 5VP 4 to the selection circuit 6, and an SVP command indicating whether it is an instruction or an operand is sent to the SVP command control circuit 7. The SVP command control circuit 7 decodes this S P command, and when the input to the selection circuit 6 is an instruction and an operand, sends out a control signal instructing the output to the instruction buffer 8 and operand buffer 9, respectively. do. In this way, instructions and operands are stored in instruction buffer 8 and operand buffer 9, respectively.

When instructions and operands have been stored in the instruction buffer 8 and operand buffer 9, the 5VP4 to SV
A command for activation is sent to the P command control circuit 7, and the SVP command control circuit 7 instructs the vector instruction generation control circuit 10 to activate the execution of the vector instruction, thereby performing a vector operation.

The vector instruction management unit 11 manages the execution status of vector operations, and when all instructions stored in the instruction buffer have been executed, transmits the completion of instruction execution to the 5VP 4 via the SvP command control circuit 7. .

5VP4 sets a new command group.

The above operations of the vector unit 3 are controlled by the operation of the 5VP4 independently of the CPUI.

〔Effect of the invention〕

According to the present invention, since it is possible to test the internal operation of the vector unit independently of the operation test of the CPU, it is possible to shorten the operation test period of the entire supercomputer system, and it is possible to conduct tests from manufacturing to product shipment. It becomes possible to significantly shorten the process.

Claims (1)

[Claims] 1. A first processor that processes a first type of instruction itself and transfers a second type of instruction to another; and a second type of instruction that is transferred from the first processor. and an external device that supplies a second type of instruction to the second processor, and the second processor processes the output of the first processor and the external device. A data processing device comprising: selection circuit means for selecting one of the outputs of the device; and buffer register means for storing the output of the selection circuit means. 2. The data processing apparatus according to claim 1, further comprising means for controlling the selection operation by the selection circuit means by a command from the external device. 3. The selection circuit means has at least one selection circuit, and the buffer register means has at least one instruction and operand buffer register pair each connected to an output of each selection circuit. Item 2. The data processing device according to item 2. 4. means for controlling the selection operations of each of the at least one selection circuit to be performed simultaneously by a command from the external device; and means for controlling the output of each selection circuit to the instruction buffer register and the operand buffer register. 4. The data processing apparatus according to claim 3, further comprising means for controlling from said external device which one of said data processing apparatuses to store data. 5. The data processing apparatus according to claim 3, further comprising means for starting processing of a group of instructions stored in said buffer register means in response to a command from said external device. 6. The data processing apparatus according to claim 5, further comprising means for notifying the external device from the second processor that processing of the instruction group stored in the buffer register means has been completed.