JPH09282165A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the interruption masking control of a cycle unit without being accompanied by the increase of the resources of an instruction memory or the like and the deterioration of a processing speed in an information processor for parallelly executing processings in plural arithmetic circuits based on an LIW instruction or a VLIW(very long instruction word) instruction for specifying the parallelly executable plural processings. SOLUTION: This processor is provided with an interruption control part 1, the instruction memory 2, an instruction decoding part 3, a register part 4, the arithmetic circuit A5 and the arithmetic circuit B6 and bypasses the arithmetic result of the arithmetic circuit A5 to the arithmetic circuit 136 through a signal line 104 for bypassing. In this case, an the case that the instruction decoding part 3 judges that interruption masking is to be performed as the result of instruction decoding, masking signals are outputted through the signal line 101 to the interruption control part 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for executing processes in parallel by a plurality of arithmetic circuits based on a LIW instruction or a VLIW instruction designating a plurality of processes that can be executed in parallel.

[0002]

2. Description of the Related Art In recent years, LIW (Long Instruction Worth)
d) type or VLIW (Very Long Instruction Word) type, etc., the specification of multiple processes that can be executed in parallel is statically described in the instruction code, and is specified by using multiple arithmetic circuits during execution. Information processing apparatuses that perform such processes in parallel have been widely used. The conventional operation of such an information processing apparatus will be briefly described below.

FIG. 7 is a block diagram showing an example of the configuration of a conventional LIW type information processing apparatus. The information processing apparatus shown in the figure includes an interrupt control unit 1, an instruction memory 2, an instruction decoding unit 3, a register unit 4, an arithmetic circuit A5, and an arithmetic circuit B6. The interrupt control unit 1 uses the interrupt signal input line 10
An interrupt signal from the outside sent through 0 is accepted and interrupt control for the information processing device is performed.

The instruction decoding unit 3 decodes an instruction code (hereinafter referred to as "LIW instruction") stored in the instruction memory 2 and, according to the decoded result, an arithmetic circuit A5 and an arithmetic circuit B6.
Control and read / write control of the register unit 4 are performed. The register unit 4 is composed of a plurality of registers, and transmits data to the arithmetic circuits A5 and B6 through the data data bus 103 according to the instruction decoding unit 3.

The arithmetic circuits A5 and B6 execute arithmetic operations based on the data sent from the data bus 103. The calculation result is written back to the register unit 4 through the data bus 105. Arithmetic circuit A5 and arithmetic circuit B
The input side of 6 is provided with pipeline latches 201 and 202 for latching the data read from the register unit 4, respectively, and between the arithmetic circuit A5 and the arithmetic circuit B6. A signal line 104 that bypasses and transmits the calculation result is provided so that the calculation circuit B6 can execute the calculation by using the calculation result in A5. In the pipeline latch 202, the data from the register unit 4,
Which of the calculation results of the calculation circuit A5 is latched is controlled by the selector 203. The selection of the selector 203 is configured to be controlled based on the decoding result of the instruction decoding unit 3.

The operation of the information processing apparatus configured as described above will be described below. FIG. 8 shows the arithmetic circuit A.
5 shows an example of the LIW instruction executed by the arithmetic circuit B6. The LIW instructions are executed in order from the top, and the horizontal row of instructions are executed in parallel by the two arithmetic circuits. add,
sub, mul, and nop are operation types of instructions executed by the respective operation circuits. Note that nop indicates that nothing is executed in the arithmetic circuit.

% G0 to% g7 indicate register names provided in the register unit 4. Further,% p indicates that the calculation result of the calculation circuit A5 is supplied to the pipeline latch 202 via the signal line 104. That is, in this LIW instruction, for example, "add% g0,% g" executed by the arithmetic circuit A5 is executed.
"1,% p" means the value of register% g0 and the value of register% g1
And the value of 1 are added to bypass the operation result and supply it to the pipeline latch 202. Here, add, which is the first descriptor in the above description, is a code indicating the type of processing (hereinafter referred to as “opcode”), and the second and third descriptors% g0 and% g1 are The source register of the operation is shown, and the fourth descriptor% p shows the destination register for storing the result of the operation. The meaning given by the arrangement of the descriptors is the same in other instructions.

For the following description, the description consisting of the first to fourth descriptors will be referred to as "instruction",
Instructions that start with add are add instructions, and instructions that start with sub are sub
An instruction, an instruction starting with mul, is called a mul instruction, and a nop is called a nop instruction. However, since the nop instruction is an instruction indicating that the operation is not performed, neither the source register nor the destination register exists.

FIG. 9 is a time chart showing a process executed in each pipeline cycle when the LIW instruction shown in FIG. 8 is executed. In cycle 1 of the figure,
The instruction decoding unit 3 decodes the add instruction and the nop instruction. In this cycle, the add instruction reads the data of the registers% g0 and% g1 from the register unit 4. The nop instruction does not read the register.

In the cycle 2, the data transmitted through the data bus 103 in the cycle 1 is latched in the pipeline latches 201 and 202, and the arithmetic circuits A5 and B6 perform arithmetic operations. In this example, the add instruction is executed in the arithmetic circuit A5, but the arithmetic circuit B6 is executed.
Then there is no operation to perform. In cycle 2, the next instruction, the sub instruction or the mul instruction, is also decoded. As shown in FIG. 8, since the source register of the mul instruction is% p, the operation result of the operation circuit A5 supplied through the bypass signal line 104 is latched by the pipeline latch 202 under the control of the selector 203.

In cycle 3, the sub instruction and the mul instruction are executed by the arithmetic circuits A5 and B6. Cycle 4
Actually writes back the operation result of the sub instruction to the register% g7 of the register unit 4. While executing the LIW instruction as above,
The processing when an interrupt occurs will be described below.

When an interrupt occurs, the normal program execution is temporarily stopped together with the interrupt, and a predetermined interrupt routine corresponding to the type of interrupt is executed. At this time, at the end of the interrupt, it is necessary to save the state of the processor (hereinafter referred to as “context”) at the time of the interrupt so that the execution can be restarted from the time of the interrupt. Generally, a processor status register (hereinafter referred to as “PS
(Abbreviated as “R”) is saved in a storage location that is not updated by the interrupt processing, and after the interrupt processing is completed, it is necessary to restore these to the original state.

Further, when performing an operation using a register in the interrupt process, it is necessary to save the register used in the interrupt process. Here, in the pipeline processing as shown in FIG. 9, it is assumed that an interrupt occurs in cycle 1, for example. As described above, in the cycle 1, the add instruction and the nop instruction are being decoded by the instruction decoding unit 3, and both the instructions are not yet executed on the arithmetic circuit.
Therefore, these instructions are decoded again by the instruction decoding unit 3 after the completion of the interrupt routine, and are executed by the arithmetic circuits A5 and B6.

On the other hand, if an interrupt occurs in cycle 2, the sub instruction and the mul instruction are decoded again by the instruction decoding unit 3 after the interrupt routine is completed, and the arithmetic circuits A5 and B6 perform arithmetic processing. However, since the add instruction decoded in cycle 1 is not processed again after the interrupt routine is completed, it is necessary to save the operation result of the instruction.
This is because the value of the source register will be lost when the mul instruction is executed after the interrupt routine ends unless the operation result of the add instruction is saved. In order to deal with such a case, the information processing apparatus of FIG. 7 is configured so that the pipeline latch 202 is duplicated and can be switched and used when an interrupt occurs.

Further, in order to reduce the overhead of save processing when an interrupt occurs and suppress the increase in resources required for save, there is a method of using an interrupt mask especially in an information processing apparatus having only one arithmetic unit. It is used. In this method, an instruction for setting and canceling an interrupt mask is described in the LIW instruction stored in the instruction memory 2 so that the interrupt is controlled only when the resource saving is unnecessary. . An example of the configuration of a LIW type information processing apparatus using such a method is shown in FIG.
0 is shown.

The configuration of the information processing apparatus shown in FIG. 3 is almost the same as that shown in FIG.
2 is not duplicated, and is different in that an interrupt control signal is sent from the data bus 103 to the control register 11 provided in the interrupt control unit 1 via the signal line 106. That is, when the instruction decoding unit 3 decodes the interrupt mask setting instruction, the control register 11 provided in the interrupt control unit 1 is instructed to set the interrupt mask, and the mask bit of the control register 11 is changed. It turns on. After that, when the instruction decoding unit 3 decodes the interrupt mask release instruction, the control register 1
The mask bit of 1 is turned off and the interrupt mask is released.

By performing the above control, PS
It is possible to deal with the interrupt without increasing the resources necessary for saving the contents of R and the pipeline latch.

[0018]

However, in the above-mentioned conventional technique, if the method of saving necessary information when an interrupt occurs is used, switching is performed as the number of arithmetic circuits that can be executed in parallel increases as described above. It is also necessary to increase the number of pipeline latches, which causes a problem that the amount of resources necessary for saving information such as pipeline latches becomes enormous. On the other hand, the method of using the interrupt mask to prevent the increase of resources is LIW type or VLI.
In the W-type information processing apparatus, if the interrupt mask is controlled in the cycle unit of pipeline processing, the interrupt mask setting instruction and the cancel instruction must be frequently executed, and the instruction amount increases, so the instruction memory 2 In addition to the need to increase the size of, the overhead for executing the control instruction of the interrupt mask cannot be ignored, and there is a problem that the execution speed of the arithmetic processing may be adversely affected.

In view of the above problems, the present invention provides an information processing apparatus capable of performing interrupt mask control in cycle units without increasing resources and affecting execution speed. The purpose is to

[0020]

In order to solve the above-mentioned problems, an information processing apparatus according to the present invention processes in a plurality of arithmetic circuits based on an instruction including designation of a plurality of processes which can be executed in parallel. In an information processing device that executes the above in parallel, outputs a control signal that decodes the instruction and realizes the plurality of processes, and outputs a mask signal that indicates whether to perform interrupt masking based on the decoding result. An instruction decoding means and an interrupt control means for controlling whether or not to accept an external interrupt according to the mask signal are provided.

The instruction includes an instruction bit for instructing whether or not to perform interrupt masking independently of designation of the plurality of processes, and the instruction decoding means is based on the state of the instruction bit. It is also possible to output a mask signal. The instruction decoding unit has a determination unit that determines whether or not to perform interrupt masking based on the contents of a plurality of processes designated by the instruction, and outputs the mask signal according to the determination of the determination unit. You can also

The information processing apparatus has at least one bypass latch for latching the calculation result of one arithmetic circuit and inputting it to another arithmetic circuit, and the judging section is included in the plurality of processes. In at least one process
When the bypass latch is designated to latch the operation result, it may be determined that the interrupt mask is performed while the process using the bypass latch is executed.

The interrupt control means may include a logical product circuit which takes a logical product of an external interrupt signal and the mask signal and outputs the logical product as an interrupt control signal. The interrupt control means further performs a logical product of a control register for instructing whether to invalidate the mask signal, an output of the control register and the mask signal, and outputs the logical product to the AND circuit. A second AND circuit, wherein the instruction decoding means further specifies the processing for canceling the invalidation of the mask signal when the instruction for decoding the instruction detects the processing for invalidating the mask signal. The control register may be set so that the mask signal is invalid until the detection.

The information processing apparatus further measures a period during which interrupt masking will be continuously performed, and when the measured period exceeds a predetermined period, the process of not performing interrupt masking is designated. An instruction assembler inserted between programs of instructions is provided, and the instruction decoding means can also decode the instructions included in the program.

The information processing apparatus further executes a process using the bypass latch when at least one process included in the plurality of processes is designated to latch the operation result in the bypass latch. A measuring unit that measures a period, a period determining unit that determines whether the period measured by the measuring unit is a predetermined period or more, and a period determining unit determines that the period is a predetermined period or more. In this case, an instruction assembler having an inserting means for inserting a designation of a process in which an interrupt mask is not performed between programs consisting of the instructions, wherein the instruction decoding means decodes the instructions included in the program. You can also

[0026]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of an information processing apparatus of this embodiment. The information processing apparatus of FIG. 1 includes an interrupt control unit 1, an instruction memory 2, an instruction decoding unit 3,
The register unit 4, the arithmetic circuit A5, the arithmetic circuit B6, and the AND circuit 7 are provided. The arithmetic circuit A5 and the arithmetic circuit B6 are connected to pipeline latches 201 and 202, respectively, and the pipeline latch 202 is connected to a selector 203.

Reference numeral 100 in the drawing denotes an interrupt signal input line to which an interrupt signal from the outside is input, 101 denotes a signal line for transmitting a mask signal output from the instruction decoding unit 3, and 10
Reference numeral 2 is a signal line for sending the decoding result of the instruction decoding unit 3 to the register unit 4, 103 and 105 are data buses, and 104 is for sending the operation result of the arithmetic circuit A5 to the pipeline latch 202 connected to the arithmetic circuit B6. Signal line.

The interrupt controller 1 controls interrupts to the information processing device based on the output of the AND circuit 7.
Specifically, when the output signal of the AND circuit 7 is on, it is detected that an interrupt signal to the information processing device is generated.
That is, even if the interrupt signal sent through the interrupt signal input line 100 is turned on, if the mask signal from the instruction decoding unit 3 sent through the signal line 101 is turned on, the interrupt request to the information processing device is not accepted. become.

The instruction decoding unit 3 decodes the LIW instruction stored in the instruction memory 2 and outputs the decoded result to the signal line 10.
In addition to being sent to the register unit 4 via 2, the mask signal for instructing to perform interrupt masking is sent to the AND circuit 7 via the signal line 101 based on the content of the decoded instruction. The instruction decoding unit 3 in the figure is configured to turn on a mask signal when performing interrupt masking.

The register section 4 is composed of a plurality of registers, and transmits data to the arithmetic circuits A5 and B6 via the data bus 103 according to the instruction decoding information sent through the signal line 102. The arithmetic circuits A5 and B6 execute arithmetic operations based on the data sent through the data bus 103 and the signal line 104, and write the arithmetic results back to the register unit 4 through the data bus 105. The input sides of the arithmetic circuit A5 and the arithmetic circuit B6 are provided with pipeline latches 201 and 202 for latching the data read from the register unit 4, respectively.
Further, between the arithmetic circuit A5 and the arithmetic circuit B6, the signal line 1 for transmitting the arithmetic result by bypass so that the arithmetic circuit B6 can execute the arithmetic operation using the arithmetic result of the arithmetic circuit A5.
04 is provided. In the pipeline latch 202,
Which of the data from the register unit 4 and the calculation result of the calculation circuit A5 is latched is controlled by the selector 203. The selection of the selector 203 is performed based on the decoding result of the instruction decoding unit 3.

The operation of the information processing apparatus configured as described above will be described below. LI as shown in FIG.
When executing the W instruction, as shown in FIG. 2, a 1-bit instruction bit indicating whether or not to perform interrupt masking is added to the LIW instruction. For example, as an instruction bit for each LIW instruction, if it is necessary to mask an interrupt when the instruction is executed, the instruction bit is set to "1", and if the instruction allows interrupts, the instruction bit is "0". Then, it is converted into a machine language program including instruction bits by the instruction assembler.

When the instruction decoding unit 3 decodes the instruction at the time of execution, that is, in the DECODE phase of each LIW instruction, if the instruction bit is "1", the mask signal output to the signal line 101 is output. It is turned on, and if the instruction bit is "0", the mask signal is turned off. Here, the setting of the instruction bit will be described more specifically. For example, when bypassing the calculation result of the calculation circuit A5 for use in the calculation circuit B6, that is,% p is designated as the destination register in the instruction sequence. In this case, the instruction bit is set to "1", and thereafter, the control bit is set to "1" until the operation in the arithmetic circuit B6 using the bypassed data is completed, and the operation circuit B6 is instructed to end the arithmetic operation. Consider the bit to be "0" at the programming stage and L
Create an IW instruction. The instruction bit can be set at an arbitrary position, and the interrupt mask can be set at the time other than the execution of the operation by bypass.

By performing the above processing, for example, in the case where an unlimited number of interrupts are acknowledged, it is possible to suppress an increase in information saving resources due to an increase in the number of bypass pipeline latches as the number of arithmetic circuits increases. At the same time, it is possible to prevent the size of the instruction memory 2 from expanding due to the description of the interrupt control instruction in the LIW instruction, and it is possible to perform interrupt control in a fine processing unit for each pipeline cycle. (Second Embodiment) FIG. 3 is a block diagram showing a configuration of an information processing apparatus according to a second embodiment of the present invention.

The configuration of the information processing apparatus shown in the figure is almost the same as that described in the first embodiment, except that the instruction decoding section 3 is provided with a judging section 31. Hereinafter, description will be made focusing on the different parts.
Although the instruction bit is described in the LIW instruction in the first embodiment, the instruction bit is not provided in the present embodiment. Instead, in the determination unit 31, for example, the signal line 10
It is determined whether or not the bypass process using 4 is to be performed, and based on the determination result, a mask signal that indicates whether or not to perform interrupt masking is output to the signal line 101.

For example, in the case of the LIW instruction as shown in FIG. 8, the mask signal output to the signal line 101 is turned on when the determination unit 31 detects that% p is designated as the destination register. After that, interrupt masking is performed until the end of the operation using the bypassed data. It should be noted that, as a criterion for the determination by the determination unit 31, other than the determination based on whether or not the bypass process is performed with reference to the designation of the destination register as described above, the determination may be performed based on the type of the operation code. Then
It is also possible to combine the operation code and the operand and use them for the determination.

With the above configuration, it is possible to perform interrupt control for each pipeline cycle without setting the instruction bit for each instruction. (Third Embodiment) FIG. 4 is a block diagram showing the configuration of an information processing apparatus according to the third embodiment of the present invention.

The configuration of the information processing apparatus shown in FIG. 11 is almost the same as that described in the second embodiment, but the control register 8
And the point that the AND circuit 9 is provided, and the data bus 1
Signal line 1 for outputting a control signal from 03 to the control register 8
The difference is that 06 is provided. Hereinafter, description will be made focusing on the different parts. Embodiment 2
In the above, the method of outputting the control signal based on the result of the determination by the determination unit 31 is used. However, depending on the content of the processing, even if the same kind of processing is performed, the interrupt mask may or may not be performed. There can be mixed cases. For example, since it may be possible that the interrupt mask does not necessarily have to be performed even in the case of the calculation using the bypass, the information processing apparatus according to the present embodiment specifies that the interrupt mask should not be performed in such a case. It is possible to use the instruction to perform. That is, when the control register 8 is installed and the instruction decoding unit 3 detects an instruction to instruct the mask signal output from the determination unit 31 to be invalid, the control bit 8a included in the control register 8 is detected. Is set to "0". The output of the AND circuit 9 is ANDed
By inputting to the circuit 7, the interrupt mask can be prohibited regardless of the determination of the determination unit 31.
After that, when an instruction for canceling the invalidation of the mask signal is detected and "1" is set in the control bit 8a, the interrupt mask is controlled again by the determination of the determination unit 31.

By performing the above-described processing, for example, the instruction should be interrupt masked in the normal state, but it is not necessary to perform the interrupt masking when judging from the entire processing contents. It is possible to deal with the case. (Embodiment 4) The processing contents of the information processing apparatus according to the present embodiment are applicable to any of the configurations of the information processing apparatus described in Embodiments 1 to 3. That is, in the information processing device of the present embodiment, the instruction assembler provided in the information processing device
A machine language program generated from a LIW instruction by automatically inserting an instruction to allow an interrupt when it is detected that the interrupt mask will be continuously performed for a predetermined period. Make a correction to.

The processing contents of the instruction assembler provided in the information processing apparatus of this embodiment will be described below. FIG. 5 is a flow chart showing the processing contents of the instruction assembler provided in the information processing apparatus of this embodiment. First, the instruction assembler resets a counter for measuring the period during which the interrupt mask is performed (S501), and L
Read the IW command (S502). If the processing has been completed for all LIW instructions, the processing of the instruction assembler is completed (S503: Yes). If not completed, the instruction assembler determines whether the read LIW instruction is an instruction requiring an interrupt mask (S504),
If the instruction does not require an interrupt mask, step S
Return to 501. If the instruction requires an interrupt mask, 1 is added to the counter value (S505). Whether or not the interrupt mask is necessary is determined based on the processing content of the instruction decoding circuit 3 when executing the processing in the information processing device after the conversion into the machine language program.

After the counter value is added in step S505, it is determined whether the counter value exceeds a predetermined value (S506). If the counter value is not exceeded, the next instruction is read. Therefore, the process returns to step S502, but if it exceeds the predetermined value, an instruction permitting the interrupt mask is inserted (S507). Specifically, insert the nop instruction in such a way that interrupt mask is not performed.

The operation of the instruction assembler which performs the above processing will be described below with reference to a specific example. When converting an LIW instruction as shown in FIG. 6A into a machine language program using the instruction assembler of this embodiment, the conversion is performed under the following conditions. That is, LIW
In at least one of the processes included in the instruction, the counter is incremented when it is determined that the interrupt mask is required for the process that bypasses the operation result (when% p is specified as the destination register). When the counter value exceeds 3, a nop instruction is inserted.

In this case, the processing contents of the machine language program output from the LIW instruction of FIG. 6 (a) are as shown in FIG. 6 (b). That is, when the LIW instruction in line (d) is read, the value of the counter exceeds 3.
The nop instruction is inserted in the form shown in the line (d ′) and line (d ″) of (b). By performing the above processing, for example, an instruction for controlling the device It is possible to avoid the occurrence of a situation in which a process that must be interrupted, such as when executing, is unable to be executed due to a long interrupt mask.

In the description of the present embodiment, an example of application to an LIW type information processing device having two arithmetic circuits has been described, but the same application is applied to a VLIW type device in which the number of arithmetic circuits is further increased. Is possible. Further, in this embodiment, the interrupt mask control is realized by using two AND circuits, but the interrupt mask control method is not limited to this.

[0044]

As is apparent from the above description, the information processing apparatus according to the present invention is information for executing processing in parallel by a plurality of arithmetic circuits based on an instruction including designation of a plurality of processing that can be executed in parallel. The processor decodes the instruction,
An instruction decoding unit that outputs a control signal that realizes the plurality of processes and outputs a mask signal that indicates whether or not to perform interrupt masking based on the decoding result, and accepts an external interrupt according to the mask signal. Interrupt control means for controlling whether or not the instruction decoding means instructs the interrupt control means whether or not to perform interrupt masking separately from the control signal for realizing the processing specified by the instruction. By outputting a mask signal for controlling the interrupt mask, it is possible to control the interrupt mask on an instruction-by-instruction basis without writing an instruction for controlling the interrupt mask in the program. The effect is that interrupt mask control can be performed in pipeline cycle units without affecting the execution speed.

Further, the instruction includes an instruction bit for instructing whether or not to perform interrupt masking independently of designation of the plurality of processes, and the instruction decoding means is based on the state of the instruction bit. It is possible to output the mask signal. In this case, since an instruction bit is provided in the instruction independently of the processing designation and the instruction bit is set at the programming stage, it is possible to control the interrupt mask in small processing units. effective.

Further, the instruction decoding means has a judging section for judging whether or not to carry out an interrupt mask based on the contents of a plurality of processes designated by the instruction, and according to the judgment of the judging section, It is also possible to output a mask signal. In this case, since the determination unit determines whether or not to perform the interrupt mask based on the content of the process, it is possible to perform the interrupt mask control without setting the control bit.

Further, when the information processing device has at least one bypass latch for latching the operation result of one arithmetic circuit and inputting it to another arithmetic circuit, the judging section is configured to operate the plurality of the plurality of arithmetic circuits. In at least one of the processes included in the process 1, it is possible to determine that the interrupt mask is performed while the process using the bypass latch is executed when the operation result is designated to be latched in the bypass latch. Is. By doing this,
Even if an interrupt may occur while executing the arithmetic processing using the bypass latch, it is not necessary to save the contents of the bypass latch.

The interrupt control means calculates a logical product of an interrupt signal from the outside and the mask signal,
It is possible to include an AND circuit that outputs as an interrupt control signal. With such a configuration, the present invention can be implemented with a simple circuit. Further, the interrupt control means further includes a control register for instructing whether to invalidate the mask signal,
The instruction decoding means further comprises a second logical product circuit that takes a logical product of the output of the control register and the mask signal and outputs the logical product to the logical product circuit. When the designation of the process for invalidating the mask signal is detected, the control register can be set to invalidate the mask signal until the designation of the process for canceling the invalidation of the mask signal is detected. It is possible. With such a configuration, particularly when the determination unit is provided and the method of controlling whether or not the interrupt mask is performed based on the content of the processing specified by the instruction, the content of the processing is the same. Even if there is, there is an effect that more efficient interrupt mask control can be performed in the processing in which the interrupt mask should be performed and the interrupt mask need not be performed.

Further, the information processing apparatus further measures a period during which interrupt masking will be continuously performed, and when the measured period exceeds a predetermined period, designation of processing in which interrupt masking is not performed is performed. And an instruction assembler which inserts between the programs including the instructions, and the instruction decoding means can decode the instructions included in the program. As described above, the instruction assembler simulates the determination contents of the instruction decoding means at the time of program execution, and if the interrupt mask is determined to be performed for a long period of time, the instruction is not interrupt masked in the program. By the insertion, the effect that the interrupt processing that is absolutely necessary is not disturbed by the interrupt mask is obtained.

The information processing apparatus further executes a process using the bypass latch when at least one process included in the plurality of processes is designated to latch the operation result in the bypass latch. A measuring unit that measures a period, a period determining unit that determines whether the period measured by the measuring unit is a predetermined period or more, and a period determining unit determines that the period is a predetermined period or more. In this case, an instruction assembler having an inserting means for inserting a designation of a process in which an interrupt mask is not performed between programs consisting of the instructions, wherein the instruction decoding means decodes the instructions included in the program. Is also possible. With such a configuration, it is possible to avoid a situation in which an interrupt mask interferes with necessary interrupt processing, particularly in an information processing device that performs arithmetic processing using a bypass latch.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device according to a first embodiment of the present invention.

FIG. 2 is a LIW used in the first embodiment of the present invention.
It is a figure which shows an example of an instruction.

FIG. 3 is a block diagram showing a configuration of an information processing device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an information processing device according to a third embodiment of the present invention.

FIG. 5 is a flowchart showing the processing contents of an instruction assembler provided in the information processing apparatus according to the fourth embodiment of the present invention.

FIG. 6A is a diagram showing an example of a LIW instruction input to the instruction assembler used in the fourth embodiment of the present invention. 7B is a diagram showing an example of processing contents of a machine language program output when the LIW instruction shown in FIG. 6A is processed by the instruction assembler of the fourth embodiment.

FIG. 7 is a block diagram showing a configuration in a case where the pipeline latch is duplicated in the conventional information processing apparatus.

FIG. 8 is a diagram showing an example of a LIW instruction.

9 is a diagram showing a case where the LIW instruction shown in FIG. 8 is executed,
6 is a time chart showing instructions executed in each pipeline cycle.

FIG. 10 is a block diagram showing a configuration when a control register is used in a conventional information processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 interrupt control part 2 instruction memory 3 instruction decoding part 31 determination part 4 register part 5 arithmetic circuit A 6 arithmetic circuit B 7 AND circuit 8 control register 8a control bit 9 AND circuit 100 interrupt signal input lines 101 to 102 signal lines 103, 105 Data bus 104, 106 Signal line 201-202 Pipeline latch 203 Selector

Claims (8)

[Claims] 1. An information processing apparatus that executes a process in parallel by a plurality of arithmetic circuits based on an instruction including designation of a plurality of processes that can be executed in parallel, and decodes the command to realize the plurality of processes. An instruction decoding unit that outputs a control signal and outputs a mask signal that indicates whether or not to perform interrupt masking based on the decoding result, and an interrupt that controls whether or not to accept an external interrupt according to the mask signal. An information processing apparatus comprising: a control unit. 2. The instruction includes an instruction bit for instructing whether or not to perform interrupt masking independently of designation of the plurality of processes, and the instruction decoding means is based on a state of the instruction bit. The information processing apparatus according to claim 1, wherein the mask signal is output. 3. The instruction decoding means includes a determination unit that determines whether or not to perform interrupt masking based on the contents of a plurality of processes designated by the instruction, and according to the determination of the determination unit, the determination unit The information processing apparatus according to claim 1, wherein the information processing apparatus outputs a mask signal. 4. The information processing device has at least one bypass latch for latching a calculation result of one calculation circuit and inputting the calculation result to another calculation circuit. In at least one process included in the above, when it is specified that the operation result should be latched in the bypass latch, it is determined that the interrupt mask is performed while the process using the bypass latch is executed. The information processing apparatus according to claim 3. 5. The interrupt control means includes a logical product circuit for calculating a logical product of an interrupt signal from the outside and the mask signal and outputting the logical product as an interrupt control signal. The information processing device according to any one of claims. 6. The AND control circuit further calculates a logical product of a control register for instructing whether to invalidate the mask signal, an output of the control register and the mask signal, and the AND circuit. A second AND circuit for outputting the mask signal, and the instruction decoding unit further cancels the invalidation of the mask signal when the instruction of decoding the instruction detects the designation of the processing for invalidating the mask signal. The information processing apparatus according to claim 5, wherein the control register is set so as to invalidate the mask signal until the designation of the processing to be performed is detected. 7. The information processing apparatus further measures a period during which interrupt masking will be performed continuously, and specifies a process in which interrupt masking is not performed when the measured period exceeds a predetermined period. 7. The information processing apparatus according to claim 1, further comprising: an instruction assembler for inserting a program including the instruction into the program, wherein the instruction decoding unit decodes the instruction included in the program. . 8. The information processing apparatus further performs a process of using the bypass latch when at least one process included in the plurality of processes is designated to latch an operation result in the bypass latch. A measuring unit that measures a period to be executed, a period determining unit that determines whether or not the period measured by the measuring unit is a predetermined period or more, and the period determining unit determines that the period is a predetermined period or more. An instruction assembler having an inserting unit that inserts a designation of a process in which the interrupt mask is not performed between the programs including the instruction, the instruction decoding unit decoding the instruction included in the program. The information processing apparatus according to claim 4, wherein the information processing apparatus comprises: