KR100194263B1 - High speed data processing system - Google Patents

Abstract

The present invention relates to a high speed data processing system.

The present invention uses the 82596 DX processor as the LAN controller 20 and control signals for controlling its operation according to the instruction of the CPU 10 ( And control logic 70 for generating CA).

The interface circuit of the present invention is economical since the conventional SRAM for buffer (60 in FIG. 1) is unnecessary and the performance of the system is improved because the CPU 10 and the LAN controller 20 share the main memory 30. .

Description

High speed data processing system

1 is a conventional data processing system employing an 82586 processor as a LAN controller.

2 is a data processing system of the present invention employing a 82596 DX processor as a LAN controller.

* Explanation of symbols for main parts of the drawings

10: CPU 20: LAN Controller

30: main memory 40: DMA buffer

50: DMA controller 60: SRAM buffer

70: control logic

The present invention relates to a high speed data processing system, such as a workstation.

Recently, Intel's 80860 microprocessor, a reduced instruction set computer (RISC) microprocessor, is widely used as a workstation CPU.

FIG. 1 shows a conventional data processing system using an 82586 processor as a LAN controller, in which 10 is a CPU, 20 is a LAN controller 82586, 30 is a main memory, and 40 is a DMA buffer. Access buffer), 50 is a DMA controller, and 60 is a static RAM (SRAM) buffer.

A case where the CPU 10 and the LAN controller 20 interface in a conventional data processing system will be described below with an example where the CPU 10 intends to transfer a command to the LAN controller 20. .

First, the CPU 10 writes commands to be transmitted to the LAN controller 20 in a predetermined area in the main memory device 30.

CPU 10 then informs DMA controller 50 that the commands to be sent to LAN controller 20 have been written into main memory 30 and instructs LAN controller 20 to deliver the commands.

In response to such a CPU 10 instruction, the DMA controller 50 transfers the instructions of the CPU 10 stored in the main memory 30 to the DMA buffer 40.

The DMA controller 50 then notifies the LAN controller 20 that the commands to be executed are stored in the DMA buffer 40 and instructs them to perform the commands.

At this time, the DMA controller 50 allows the LAN controller 20 to use the DMA bus according to the instruction of the CPU 10.

Therefore, the LAN controller 20 fetches and executes a command stored in the DMA buffer 40.

Subsequently, after completing the execution of the command, the LAN controller 20 provides an interrupt signal to the CPU 10 through the DMA controller 50 to release the DMA bus used during the execution of the command at the same time as notifying that the execution of the command is completed. (release)

At this time, the CPU 10 analyzes the status of the command execution result transmitted from the LAN controller 20 through the DMA bus, confirms that the command execution is completed, and terminates the interface.

As described above, in the conventional interface circuit, the CPU and the LAN controller cannot directly interface because the CPU and the LAN controller cannot share the main memory.

Therefore, the interface time between the CPU and the LAN controller is long, there is a problem that the efficiency of the system is reduced.

In addition, since the 82586 processor used as the conventional LAN controller 20 is a processor that does not support the ability to directly access the main memory, data is inputted from the LAN to the data processing system or data is transferred to the data processing system. When output, the high speed CPU 10 had to process the data directly.

Therefore, to prevent the performance degradation of the system, a buffer was needed to temporarily store the data until the CPU processed the data related to the LAN.

In order to store such data, in the conventional interface circuit, SRAM is used as the LAN buffer 60. However, since the SRAM is expensive, the price of the product has been raised.

Therefore, the present invention simplifies the configuration of the system and employs the 82596 DX processor as a LAN controller that supports the function of sharing the data path and address path of the main memory on the same basis as the CPU. The purpose is to improve.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 2 shows a data processing system of the present invention.

In the figure, 10 is CPU, 20 is LAN controller, 82596 DX processor, 30 is main memory, 70 is control logic.

Inside the 82596 DX processor, which is the LAN controller 20, a command unit (21) for executing commands, and a receive unit for inputting data from the LAN cable to the data processing system or outputting data from the system to the LAN. (22)

As described above, a case where the CPU 10 and the LAN controller 20 interface with each other as a case where the CPU 10 transfers commands to the LAN controller 20 will be described below.

First, the CPU 10 writes commands to be transmitted to the LAN controller 20 in a predetermined area in the main memory 30.

The CPU 10 then loads the start address of the place where the instructions are stored on the data bus and provides a control signal to the control logic 70 so that the control logic 70 can be loaded. The signal is transmitted to the LAN controller 20.

The CPU 10 also provides the LAN controller 20 with an HLDA signal allowing the use of the bus.

Output from the control logic 70 The signal informs the LAN controller 20 that the commands transmitted from the CPU 10 to the LAN controller 20 are stored in the main memory 30, and the start address of the command data block is loaded on the data bus at the same time. Inform.

Accordingly, the LAN controller 20 fetches the contents of the main memory from the start address of the command data block transmitted from the CPU 10 into an internal 32-bit buffer register.

When the data fetch of the LAN controller 20 is completed, the CPU 10 again provides a control signal to the control logic 70 to generate a CA (Command Attention) signal for causing the LAN controller 20 to execute the fetched commands. do.

By the CA signal output from the control logic 70, the LAN controller 20 executes the instructions indicated by the CPU 10 from the start address.

At this time, command execution is performed by the command unit 21 in the LAN controller 20.

After the command execution is completed, the LAN controller 20 provides the CPU 10 with a signal for releasing the bus used during the command execution.

At this time, the CPU 10 analyzes the status of the instruction execution result, confirms that the instruction execution is completed, and terminates the interface.

On the other hand, the CA signal for causing the LAN controller 20 to execute the command blocks stored in the main memory is an internally synchronized signal and a high state is maintained for at least one system clock.

When the CA signal is latched from the high state to the low state, the LAN controller 20 starts to execute the command block.

The first CA signal generated after the reset causes instruction execution to begin from the System Configuration Pointer (SCP) address of the 82596 DX processor using address 00FFFFF6 of the main memory or CPU port access.

As described above, the data processing system of the present invention improves the performance of the system by using the 82596 DX processor, which shares the main memory equally with the CPU, as a LAN controller, and is economical because it does not require expensive SRAM buffers. There is an advantage that can secure more free space on the bed.

Claims (2)

In a data processing system comprising at least a CPU 10, a LAN controller 20, a main memory 30, and a plurality of buses, the LAN controller 20, together with the CPU 10, the main memory device. 30 is connected to the main memory device 30 so as to share 30, and is connected between the CPU 10 and the LAN controller 20 to control the LAN controller 20 by the control output signal of the CPU 10. Control signals for controlling the operation ( And control means (70) for providing a CA to the LAN controller (20). 2. The high speed data processing system as claimed in claim 1, wherein said LAN controller (20) is an 82596 DX processor.