JPS6212540B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer debugging device, and in particular, to a debugging device including a small computer device, when the need for debugging arises, the debugging device can be debugged without disturbing the control operation of the debugged device.
Furthermore, it is a debugging device that can extract various data necessary for debugging at high speed, making real-time debugging possible.

Generally, an automatic control device incorporates a relatively small computer such as a microcomputer to perform automatic control operations based on a preset program. In such an automatic control device, when an abnormality occurs or when maintenance is performed, it is necessary to investigate the cause of the abnormality by reading out data that is being processed based on the sequence of operations of the computer.

One method is to use an address comparator,
When the address of the debugged device matches the set address, an address match signal is generated, which interrupts the operation of the debugged device.
A method has been proposed in which an interrupt service program is executed and necessary data is displayed on an output device.

However, in order to reduce costs, automatic control devices built into computers generally do not have address comparators or input/output devices necessary for debugging, nor do they have interrupt service programs. Furthermore, since the operation of the input/output device is much slower than that of the computer itself, when the above-mentioned debugging was carried out, there was a serious drawback in that the original operation of the automatic control device had to be interrupted during that time.

The present invention has been proposed in view of the above-mentioned problems, and provides a debugging device that can retrieve desired memory locations and register contents from the outside without affecting the operation of the debugged device. be.

The present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and A is a computer device to be debugged (device to be debugged).
A memory 3 is connected to a central processing unit (CPU) 1 and a data bus DB of the CPU 1 via a bidirectional bus buffer 2, and stores programs in which processing procedures of the CPU 1 are set in advance and input/output data.
and an input/output interface 4 for connecting a CPU 1 and an automatic control device B controlled by the CPU 1. C is a debugging device according to the present invention, and 5 is a computer device having the same configuration as the device to be debugged A, which is connected to the CPU 6 and the data bus DB of the CPU 6 via a bidirectional bus buffer 7, and is used for inputting address data and displaying output. It includes a memory 8 that stores debug programs such as programs, and an input/output interface 11 that connects an input device 9 and an output device 10 to the CPU 6. and 1
2 is each of debugged device A and debugged device C.
It is connected to the data buses DB of CPUs 1 and 6 via bidirectional bus buffers 13 and 14, and stores and transfers programs necessary for debugging, such as transfer programs that transfer data in the registers of CPU 1 and data in memory 3. 15 is a command generation section that is set in advance to generate a specific command; for example, the common memory 1
This command generates a call instruction to call the debugging subroutine program No. 2. and 1
6 is a bus buffer that inputs the signal from the instruction generation unit 15 to the data bus DB of the CPU 1; 17 is a latch circuit that is connected to the address bus AB of the CPU 6 and latches the address data set by the input device 9; and 18 is a latch circuit. Output of circuit 17 and CPU1
19 is an RS flip-flop circuit, the output of comparator 18 is input to S input, and 19 is an RS flip-flop circuit.
The instruction fetch completion signal output of the CPU 1 of the device to be debugged 4 is connected to the R input. Each of the bus buffers 2, 7, 13, 14, and 16 is a tri-state bus buffer whose output can be put into a floating state by setting the terminal CS to the O level. I try not to affect it. While connecting the Q output of the flip-flop circuit 19 to the terminal CS of the bus buffer 16,
Bidirectional bus buffer 2 via inverter 20
is connected to terminal CS. Here, the flip-flop circuit 19 and the inverter 20 form a switching means for switching between the memory 3 and the instruction generating section 15 based on the output of the comparator 18. Further, the output of the input/output interface 11 of the computer device 5 is connected to the latch terminal L of the latch circuit 17, and the other output is connected to the terminal CS of the bidirectional bus buffer 14. It is connected to terminal CS of 13. The illustrated arrows indicate the flow of signals, and (ⓓ) indicates a plurality of signal lines.

FIG. 2 shows an example of the memory areas of the memories 3 and 8 and the common memory 12 in FIG. A program 8a for controlling C is accommodated, respectively,
The memory area of the common memory 12 is arranged in a common memory area that does not overlap with each program 3a, 8a,
A program 12a for transferring data in each register of the CPU 1 and data in the memory 3 of the debugged device A, and a data storage area 12b for storing the transferred data are set, and the bus buffers 13, 1
4, it is incorporated into either one of the memories 3 and 8.

The operation of the present invention will be explained below.

In the initial state, the Q output of the flip-flop circuit 19 is at O level, and the bidirectional bus buffer 1
Assume that terminal CS of No. 4 is at level 1. As a result, the instruction generating section 15 is separated from the CPU 1, and the output of the inverter 20 becomes 1 level, so the bidirectional bus buffer 2 becomes active and the CPU 1 and the memory 3 are connected. Also, the bidirectional bus buffer 14 becomes active, and the common memory 12 is connected to the CPU.
Since the output of the inverter 21 becomes O level, the bidirectional bus buffer 13 becomes disabled and the common memory 12 is separated from the CPU 1. Therefore, the debugged device A operates based on the program in the memory 3 and controls the automatic control device B.
Based on the program in the memory 8, the debugging device C enters a state of waiting for input data from the input device 9. Here, when the address to be checked is input using the input device 9, the address data is given from the address bus AB to the input of the latch circuit 17, and depending on the address setting, the address data is input to the input/output interface 11.
A latch signal is generated to latch the address data. At the same time, the bidirectional bus buffer 14 is disabled by the output signal of the input/output interface, and the bidirectional bus buffer 13 is enabled by the inverter 21 to read the common memory 12.
Connect to CPU1. In this state, as the debugged device A operates, the data on the address bus AB of the CPU 1 changes sequentially, but when it matches the address data latched in the latch circuit 17, a match output is generated at the output of the comparator 18. do. As a result, the S input of the flip-flop circuit 19 becomes 1.
level, and the Q output is held at 1 level. As a result, the bus buffer 16 becomes active, and at the same time, the bidirectional bus buffer 2 becomes disabled by the inverter 20, and the memory 3 is transferred to the CPU 1.
The call command from the command generation unit 15 is separated from
Input to data bus DB of CPU1. Since the CPU 1 takes in instructions in the instruction fetch cycle, the instruction generation section 15 is connected to the CPU 1, detects the falling edge of the instruction fetch cycle, and inputs this signal to the R input of the flip-flop circuit 19. After fetching the instruction, the output of the flip-flop circuit 19 is inverted, the Q output becomes O level, the instruction generating section is separated from the CPU 1, and the memory 3 is connected to the CPI 1 again. At this time, the CPU 1 executes the debugging program 12a in the common memory 12, and stores predetermined data in the data storage area 12b. Then, the program in the memory 3 is executed again by the return instruction at the end of the program 12a. The contents of the common memory 12 are input by an input device,
Due to the display operation, the output of the input/output interface 11 becomes 1 level, the states of the bidirectional bus buffers 13 and 14 are reversed, and the common memory 1
2 from the CPU 1 and connect it to the CPU 6 at any time, the data storage area 1 of the common memory 12
2b can be displayed on the output device 10.

Even if the device to be debugged has the minimum necessary configuration, by using the debugging device according to the present invention, the device to be debugged can be debugged by simply providing connection terminals. can. In addition, the data transfer is sufficiently short compared to the operating speed of the automatic control device, and data in the actual operating state can be obtained without stopping the original operation of the automatic control device, so it can be used not only for checking programs but also for mechanical It is also possible to debug environmental conditions such as timing and external noise, and it is possible to retrieve and display data at a desired address at any time.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and for example, a plurality of addresses can be set in advance, debugged sequentially, and displayed all at once.

As described above, according to the present invention, when it becomes necessary to debug the operation of a device to be debugged including a computer device, data to be debugged can be continuously interrupted in the sequential operation of the program of the device to be debugged. A debugging device capable of debugging in real time can be obtained by instantaneously reading data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a drawing showing an example of each memory area. A...device to be debugged, C...device to be debugged,
5...Debugging computer, 9...Input device, 10...Output device, 12...Common memory, 1
2a...Debugging program, 12b...Data storage area, 15...Instruction generation unit, 17...Latch circuit, 18...Comparator, 19, 20...Switching means.

Claims (1)

[Claims] 1 A computer for debugging, and a common memory that is selectively connected to the debugging computer including the debugging computer and the computer to be debugged, and has a data storage area for storing the debugging program and data retrieved by the debugging. , an input device for inputting data for debugging, an output device for displaying retrieved data, a latch circuit for latching the address data of the instruction requiring debugging, and the address data of the latch circuit and the device to be debugged. A comparator that compares address data, an instruction generation unit that generates an instruction to cause the device to be debugged to execute a debugging program in a common memory, and a command generation unit that connects to the computer of the device to be debugged based on the output of the comparator. A debugging device characterized by comprising a switching means.