JPS6325758A - Slave processor - Google Patents

Abstract

PURPOSE:To shorten a program loading time by providing a data buffer between an internal bus and a common bus, outputting an internal state onto a common bus via a status buffer and mapping the contents of a local memory over a common memory. CONSTITUTION:An internal bus 120 is connected to a common bus 121 via a data buffer 4 and an internal state is outputted onto a common bus 121 via a status buffer 5. A holding signal is produced so that a local CPU 1 is set by the reset signal of the bus 121 or a specific I/O instruction and then reset by another I/O instruction. Then the CPU 1 is held by said holding signal and the contents of a local memory 3 are mapped over a common memory 13.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a hardware configuration of an information processing device, and more particularly to a program loading method to a slave processor in a multiprocessor system with a master/slave processor configuration.

(Prior Art) Conventionally, a multiprocessor system with a master/slave processor configuration of this type has a sidelight configuration as shown in FIG. 2. The conventional technique will be explained below with reference to FIG.

The slave processor 200 according to the prior art is low J#0P.
U201, program ROM202, and local memory controller 203. ! :, local memory 204
, a data buffer 205 , a bus window address decoder 206 , and a local I/O instruction decoder 207
, bus request circuit 208 , first flip-flop 209 , memory command buffer 2/O, address register 211 , address buffer 212 , second flip-flop 213 , and E/O instruction decoder 2
14? In FIG. 90, 220 is an internal bus, 221ti is a common bus, 2151't is a common memory, and 216 is a master processor.

In Figure 2, when the device is powered on, the local 0
The PU 201 starts executing the programs R and OM 202 from the first instruction. Procedures necessary for program loading are written in the program ROM 202. The outline of the procedure is as summarized in the following 1st to 4th steps.

In the first step, the master processor 216 writes control # information to a predetermined area of the common memory 215, and the I/O instruction decoder 21 of the slave processor 200
4 is used to set the first flip-flop 213t.

In the second step, the first flip-flop 213
is connected to the interrupt input of the local 0PU 201, and after the local 0PU 201 recognizes all the interrupts, it takes over all the control information from the common memory 215 according to the following first to third substeps.

That is, in the first substep, local 0PU2
01 stores the storage address of the control information in the address register 211, and in the second substep local 0PU2
01 accesses the bus window address group. At this time, the bus window address decoder 206 detects the bus window address and the bus request circuit 208
At the same time, the local memory controller 203 is set to the disabled state.

In the third substep, the bus request circuit 208
acquires the entire bus, data buffer 205, memory command buffer 2/O, and address buffer 212
enable state. By this, common bus 2
A control information storage address and a memory command are output to 21, and the local 0PU 201 receives the control information.

In the third step, temperature and control information are stored in local memory 2.
Common memory 21 of the program to be loaded into 04
The storage position in 5, O and its length are stored. The local CPU 201 registers the address register 211 on the address of the common memory 215 corresponding to the above storage location.
and access the bus window address in the same way as above.

In the fourth step, when the length stored in the control a information reaches zero, the local OPU 201 uses the entire local E/○ instruction decoder 207 to set the second flip-flop 209, indicating that the load is completed. Processor 216 is notified.

The above is an outline of the operation of the conventional multiprocessor system shown in FIG.

(Problems to be Solved by the Invention) The multiprocessor system according to the conventional technique described above has the following first to third problems.

The first problem is that since the local CPU 201 loads the entire program using the bus window, the amount of data transferred at one time is limited by the bus window size. If the bus window size is increased, the capacity of the local memory 204 will be reduced by that amount, so for example, in the case of an 8-bit local CPU that uses 64 to 9 bytes of memory, the window size is generally about IK bytes. It is. On the other hand, the program size is generally much larger than the window size, with some programs reaching up to 40 bytes. Therefore, the above transfer '(j) is repeated as many as 40 times, and the transfer takes an extremely long time.

The second problem is that in order for the local 0PU 201 to access the bus, it requires a bus request circuit 208tl and also a program ROM 202, which increases the hardware cost of the slave processor 200. be.

The third problem is that it is necessary to develop a program for the slave processor 2000 that executes the interface between the master processor 216 and the slave processor 200.

In addition, the ninth problem that solves the first problem above is data transfer.
A method of performing p+ rows using a direct memory access method (DMA) is also known, but this method does not provide a solution to the second and third problems.

An object of the present invention is to connect an internal bus and a common bus through an open data buffer, output the data onto the common bus using an internal status t status buffer, and be reset by a reset signal of the common bus or a specific I/O command.
By holding the local 0PUI using a hold signal generated to be reset by the O instruction and mapping the contents of the local memory onto the common memory, the above disadvantages are eliminated, there is no need to develop related programs, and less hardware is consumed. The purpose of the present invention is to provide a slave processor that is configured so that the transfer time can be significantly shortened.

(Means for Solving the Problems) A slave processor according to the present invention has a local CPU, a data buffer, a status buffer, a flip-flop, a work/o instruction decoder, a memory address decoder, a memory command buffer, an address It is configured to include a buffer and local memory means.

The local CPU is used to form all the main parts of the multi-processor system using a master-slave configuration.

The data buffer is for connecting the data signal a″Ik between the internal bus and the common bus.

The status buffer is internal status 1! This is the one that outputs to the l4t-common bus.

Flip-flops can be reset by a specific I/O command as well as by other I/O commands using a reset signal from the common bus,
This is for holding Gocal 0PUQ when the above setting is made.

The I/O instruction decoder is for decoding all 0 I/O instructions on the common bus.

The memory address decoder is for decoding memory addresses on the common bus.

The memory command buffer is connected to the memory R/
This is for connecting to the W signal 7 internal bus.

Is the address buffer an address on the common bus? This is a friend that connects to an internal path.

Local memory means are for storing data and addresses as part of the master processor's memory space.

(real male side) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of a slave processor seven TTR multiprocessor system according to the present invention. In Figure 1, /O0 is a slave processor, l is a low power, /l/OP0.2 is a local memory controller, 3 is a local memory, 4 is a data buffer, 5 is a status buffer, and 6 is a flip-flop for hold requests. , 7 is an I/O command decoder, 8 is a memory address decoder, 9 is a memory command buffer, IO is an address buffer, 11 is an OR gate, 12 is a master processor,
13 is common memory, 120flP' [lS lotus, 12
1 u common bus steal.

In FIG. 1, an I/O instruction decoder 7 decodes I/O instructions from a master processor 12, and a memory address decoder 8 decodes all memory addresses from the master processor 12.

Memory: The mantle buffer 9 connects memory commands from the master processor 12 to the local memory controller 2, and connects the address buffer/Oi master processor 12 to all local memories 3. The OR gate 11 receives a reset signal input from the common bus 221 and an I/
The logical OR with the signal output from the O instruction decoder 7 is calculated.

When the device is powered on and a reset signal is input from the common bus 121, the flip-flop 6 is turned on. The flip-flop 6 is connected to the hold terminal of the local 0PUI, and the local 0PUI is placed in the hold state as described above. When local CPU 1 is held, "Ho1d A' (f(old Ackn
OWLEDGE ) Sends f and puts all data/address/memory RW signal lines of the internal bus 120 into a high impedance state.

On the other hand, the Ho1d A signal is sent to the data buffer 4% memory command buffer 9 and the address buffer /O.
iEnable state. In this state, common bus 1
All of the 21 units (g) are connected to the internal bus 120.

(9) The memory address decoder 8 decodes a predetermined address range for the common bus 121 addresses. As a reminder, local memory 3 is connected to master processor 1.
2 memory space.

The master processor 12 uses the status buffer 5,
After confirming that the slave processor/O() is in the "Hold" state, it initiates a block transfer of data in its own memory space. Naturally, the source is the program to be transferred to local memory, and the destination is local memory 3.

(Effects of the Invention) As explained above, the present invention connects the internal bus and the common bus with the open data buffer (KLV), outputs the data on the common bus using the status buffer based on the internal state, and outputs the common bus reset signal or specific I/O signal. The local CPU'? is a hold signal generated to be set by an instruction and reset by another M/O instruction. By holding and mapping the contents of local memory onto all common memories, program load time is greatly shortened, and the need for a program ROM and path request circuit is eliminated, greatly reducing hardware costs. This has the effect of reducing the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a multiprocessor system including a master processor according to the present invention. Figure 2 is an example of a multiprocessor system including a master processor according to the prior art. FIG. 1.201... Local CPU 2.203... Local memory controller 3.20
4...Local memory 4.205...Data buffer 5...Status buffer 6.209,213...Flip frog 7.214
...I/O instruction decoder 8...Memory address decoder 9.2/O...Memory command buffer/O. 212
. . . Address buffer 11 . . . O-gate 12. 216 . . . Master processor 13. 215 .
...Local I/O instruction decoder 208...Bus request circuit 211...Address register 120.220...Internal bus

Claims (1)

[Claims] A local CPU that forms the main part of a multiprocessor system with a master/slave configuration, a data buffer that connects a data signal line between the internal bus and the common bus, and a status that outputs the internal state to the common bus. a buffer, a flip-flop that can be set by a reset signal from the common bus or a specific I/O command, and can be reset by another I/O command, and holds the local CPU when the buffer is set; , an I/O instruction decoder for decoding I/O instructions on the common bus;
a memory address decoder for decoding memory addresses on the common bus; and a memory R on the common bus.
a memory command buffer for connecting the /W signal to the internal bus, an address buffer for connecting the address on the common bus to the internal bus, and storing data and addresses as part of the memory space of the master processor. What is claimed is: 1. A slave processor characterized in that it is configured to include local memory means for.