JPH04347762A - Multi-processor system which is roughly connected with system bus - Google Patents

Abstract

PURPOSE:To obtain a multi-processor system which is roughly connected with a system bus where cost can be reduced without stopping a processor on a local bus-side at the time transferring data on a system bus-side. CONSTITUTION:DMAC (direct memory access controller) 4 stores data stored in a global memory 3 in VRAM (picture memory) 2 through the system bus 5. At that time, CPU 1 on the local bus 6-side can freely access to VRAM 2. Thus, a data processing can be executed by CPU on the local bus-side without stopping at the time of transferring data on the system bus-side, and cost can be reduced by using inexpensive VRAM.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system loosely coupled to a system bus that can easily transfer a large amount of image data without stopping the system.

0002

2. Description of the Related Art FIG. 4 is a block circuit diagram showing the configuration of a conventional multiprocessor system. In the figure, 1
are each CPU connected to the system bus 5 side or the local bus 6 side, and each CPU1 is a CPU connected to the system bus 5 side.
It processes data etc. separately from U (not shown). 3 is a global memory connected to the system bus 5 side, and the global memory 3 stores in advance a large amount of calculation data etc. necessary for each CPU 1. 4 is a DMAC (DMA Controller) connected to the system bus 5 side, which takes out calculation data etc. stored in the global memory 3 based on commands from the CPU on the system bus 5 side and stores it in a desired memory. 7 is a memory connected to the system bus 5 side, and data stored in the global memory 3 is stored in a desired memory 7 by the DMA function of the DMAC 4. 8 is a dual port memory connected to both system bus 5 and local bus 6, and DMAC 4
Data stored in the global memory 3 is stored in a desired dual port memory 8 via the system bus 5 by the DMA function. Note that the dual port memory 8 accepts accesses from the CPU on the system bus 5 side as well as from the CPU on the local bus 6 side. A local memory 9 is connected to the CPU 1 via a local bus 6, and data stored in the dual port memory 8 by the CPU 1 is stored in the local memory 9.

Since the conventional multiprocessor system is configured as described above, in FIG. 3(a) (when the system bus 5 is connected to each CPU 1 and each memory 7), for example, the system bus A large amount of calculation data etc. previously stored in the global memory 3 by the DMAC 4 on the 5 side is stored at a predetermined address in each memory 7 via the system bus 5. Then, each CPU 1 retrieves the calculation data etc. stored in the memory 7 and executes arithmetic processing etc. In addition, in FIG. 3(b), (system bus 5 and each CPU
1 local bus 6 is loosely coupled via each dual port memory 8), for example, the DM on the system bus 5 side
A large amount of calculation data etc. previously stored in the global memory 3 by the AC 4 is stored in a desired RAM (Random Access Port) of the dual port memory 8 via the system bus 5. Then, the CPU 1 accesses the data stored in the RAM and performs arithmetic processing and the like. Furthermore, Figure 3
In (c) (when the system bus 5 and the local bus 6 of each CPU 1 are loosely coupled via each dual port memory 8, and the local memory 9 is connected to the local bus 6), for example, the system bus 5 A large amount of calculation data etc. stored in advance in the global memory 3 by the side DMAC 4 is transferred to each dual port memory 8 via the system bus 5.
The data is stored in the RAM of Then, the CPU 1 temporarily stores the data stored in the RAM of the dual port memory 8 in the local memory 9 via the local bus 6, and each CPU 1 takes out the stored data and performs arithmetic processing.

0004

[Problem to be Solved by the Invention] When configured with the conventional multiprocessor system as described above, data necessary for calculation must be transferred from global memory to local memory exclusive to each processor. , at that time, the CPU on the local bus side and the CPU on the system bus side
If a dual port memory 8 that can be accessed simultaneously from U and U is used, the cost will be high, and if a memory that cannot be accessed simultaneously is used, the CPU will have to be stopped.

[0005] The present invention has been made to solve such problems, and it is possible to execute data processing without stopping the CPU on the local bus side when data is transferred on the system bus side, and to The present invention aims to provide a multiprocessor system that is loosely coupled to a system bus and that can reduce costs by using an inexpensive VRAM that is loosely coupled to a system bus.

[0006]

[Means for Solving the Problems] A multiprocessor system loosely coupled to a system bus according to the present invention is a system in which each processor, which is loosely coupled to the system bus and has each local bus, processes data. A serial access memory port is connected to the system bus, and a random access memory port is connected to the local bus, and data is stored in the global memory via the system bus. each image RAM for storing data and data from the processor via the local bus; and data stored in the global memory and the and data transfer means for mutually transferring data stored in the image RAM to the other party via the system bus.

[0007]

In the present invention, the data transfer means writes data previously stored in the global memory into the image memory via the system bus in response to a command from a processor having a dedicated image RAM via the local bus. that time,
The processor on the local bus side can freely access the image memory. Furthermore, the data transfer means stores the data processed by the local processor and stored in the image memory in the global memory via the system bus in response to a command from the processor. that time,
The processor on the local bus side can freely access the image memory.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block circuit diagram showing one embodiment of the present invention, in which numerals 1, 3, and 4 are the same as the conventional circuit. In the figure, system bus 5 is connected to one SAM (serial access memory) port 2, and RAM (
The system bus 5 and the local bus 6 of the CPU 1 are loosely coupled by the VRAM 2, and the DMA of the DMAC 4 is connected to the system bus 5.
According to the function, calculation data, etc. (including programs) stored in the global memory 3 are stored from the SAM of the desired VRAM 2 to the RAM via the system bus 5. In addition, the calculation data processed by each CPU1 is stored in the R of VRAM2.
AM, and the calculated data is stored in V by DMAC4.
The data is stored in the global memory 3 from the SAM of the RAM 2 via the system bus. Incidentally, each CPU 1 is set in advance to the DMAC 4 to perform DMA transfer between the global memory 3 and the exclusive VRAM 2.

A multiprocessor system loosely coupled to a system bus using the VRAM of the present invention is configured as described above, and FIG. 2 is a timing chart for storing calculation data stored in the global memory in the VRAM, and FIG. is a timing chart for storing data stored in VRAM into global memory, and its operation will be explained.

First, in FIGS. 1 and 2, a certain CPU
1 transfers the desired calculation data stored in global memory 3 to DMAC 4 in order to store it in dedicated VRAM 2 (between global memory 3 and VRAM 2)
After that, a pseudo write transfer is performed to put the SAM of the exclusive VRAM 2 into input mode. D
MAC4 uses system bus 5 according to a command from CPU1.
At the same time, the global memory 3 in which the calculation data is stored is addressed to retrieve the desired calculation data, and the retrieved calculation data is transferred to the SAM of the VRAM 2 via the system bus 5. write to. The calculation data written in the SAM is then transferred to the RAM of the VRAM2 by write transfer. C
For PU1, DMAC4 transfers data from global memory 3 to VRAM.
When performing DMA transfer to SAM 2, the dedicated VRAM 2 RAM can be accessed for other processing. Therefore, while executing a certain process, the CPU 1 can previously store necessary calculation data or programs in the exclusive VRAM 2 by DMA transfer by the DMAC 4.

Furthermore, in FIGS. 1 and 3, a certain CPU 1
In order to store the calculated data stored in the RAM of VRAM2 in the global memory 3 again, the CPU1 performs DMA transfer (VRAM transfer) to the DMAC4.
2 → global memory) command is output. DMAC
4 acquires the system bus right according to a command from CPU 1, and the RAM of VRAM 2 in which calculation data is stored.
Specify an address for. The VRAM reads and transfers the desired calculation data from the RAM to the SAM, and the DMAC transfers the retrieved calculation data from the SAM to the system bus 5.
The data is written to the global memory 3 via the . CPU
1, when the DMAC 4 is performing DMA transfer from the SAM of the VRAM 2 to the global memory 3, it can access the dedicated RAM of the VRAM 2 to perform other processing.

In this way, the V connected to the system bus side
Since RAM 2 uses SAM, it can only be accessed serially, but during this time, CPU 1 can access the RAM of VRAM 2 with almost no influence from the system bus. Furthermore, since data processing by the CPU 1 and transfer processing by the DMAC 4 are performed simultaneously, the time required for data transfer is hidden in the data processing time, eliminating the apparent transfer time. In addition, in the above embodiment, D
Although MAC4 is used for data transfer, the present invention is not limited to DMAC, and a processor for data transfer may be used.

[0013]

As described above, according to the present invention, the image memory is used to loosely couple the system bus and the local bus, and data is transferred between the system buses.
Data processing is performed without temporarily stopping the processor on the local bus side, and costs are reduced by using the image memory.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing one embodiment of the present invention.

[Figure 2] Calculation data stored in global memory
It is a timing chart of storing in RAM.

FIG. 3 is a timing chart for storing data stored in VRAM into global memory.

FIG. 4 is a block circuit diagram showing the configuration of each conventional multiprocessor system.

[Explanation of symbols]

1 CPU 2 VRAM 3 Global memory 4 DMAC 5 System bus 6. Local bus

Claims (1)

[Claims] Claim 1. In a system in which each processor having a local bus and loosely coupled to a system bus performs data processing, a global memory connected to the system bus and storing data in advance, and a serial memory connected to the system bus. an access memory port is connected to the local bus, and a random access memory port is connected to the local bus to store data from the global memory via the system bus and data from the processor via the local bus. The data stored in the image RAM and the data stored in the global memory and the data stored in the image RAM are mutually communicated via the system bus according to a command from the processor having the dedicated image RAM via the image RAM and the local bus. What is claimed is: 1. A multiprocessor system loosely coupled to a system bus, characterized by comprising a data transfer means for transferring data to a counterpart side.