JPH03156647A - Watchdog timer - Google Patents

Abstract

PURPOSE:To faciliate the preparation of a program by providing a means which decodes the instruction fetch cycle of a CPU and inputting the output of the decoding means to a counter to count the instruction fetch cycles of the CPU. CONSTITUTION:An instruction fetch cycle decoding means 3 outputs a pulse every time a CPU 1 carries out a program and reads an instruction out of a memory. A counter 4 counts the pulses outputted from the means 3. Therefore, the counter 4 is updated during execution of the program and not updated when the operation of the CPU 1 is stopped by the DMA transfer, etc. Thus, it is required to consider only the number of steps of the program with no consideration needed for the program executing time and the CPU stopping time when the counter reset instructions are arranged into the program. Thus, the program load is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a runaway detection method in a digital computer system.

[Conventional technology]

A conventional watchdog timer always supplies a clock with a constant cycle, for example, a signal obtained by dividing a system clock, as a clock. A known example of this type of watchdog timer is, for example, Japanese Patent Application Laid-Open No. 63-26804.
Publication No. 4, JP-A-63-271545, JP-A-6
3-316146 is mentioned.

[Problem to be solved by the invention]

The watchdog timer according to the above-mentioned prior art does not take into consideration the operation when the CPU stops executing the program. For example, when a DMA (direct memory access) transfer is being performed, the CPU suspends program execution, so no reset signal is generated for the watchdog timer. On the other hand, since pulses are always input to the clock input of the watchdog timer at a constant cycle, there is a possibility that the watchdog timer will eventually overflow and cause a watchdog timeout. Therefore, when creating a program, consider not only the program execution time.

It is necessary to place a watchdog timer reset instruction in the program while taking into account the time during which program execution is stopped, which poses a problem of increasing the burden on the program.

Furthermore, the execution time varies depending on the type of CPU instruction.

Therefore, it is necessary to place the watchdog timer reset instruction taking into account the difference in execution time of each instruction.
There was also the problem of increasing the burden on programmers.

The object of the present invention is to provide a watchdog timer that does not have the above two problems.

[Means to solve the problem]

In order to achieve the above objectives, the present invention provides means for generating one pulse for each instruction fetch cycle of the CPU instead of a constant cycle clock, and counts this pulse.

[Effect]

The instruction fetch cycle decoding means outputs one pulse each time the CPU executes a program and reads one instruction from the memory. The counter counts the pulses output by the instruction fetch cycle decoding means. Therefore, the counter is updated during program execution, but is not updated when the CPU is stopped due to DMA transfer or the like.

Therefore, when placing a counter reset instruction in a program, it is only necessary to consider the number of steps in the program, without considering program execution time or CPU stop time.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

■ is the CPU, and the address bus 11. data bus 12
, and are connected to the control bus 13. 2 is a counter reset instruction decoding means, and the address bus 11.2 is a counter reset instruction decoding means. Data bus 12. The control bus 13 is decoded and the CPU issues a predetermined command (counter reset command).
By executing this, a pulse is output to the counter reset signal line 21. 3 is an instruction fetch cycle decoding means, which outputs a pulse to the instruction fetch signal line every time the CPU 1 fetches an instruction. 4 is a counter,
While counting pulses on the instruction fetch signal line, it is reset by pulses on the reset signal line.

Further, when this counter overflows, it generates a pulse on the CPU reset signal line 41 to reset the CPU.

Instruction fetch cycle de: 1-1 to means 3 every time the CPU fetches an instruction while executing the program normally.
generates a pulse, and the counter 4 counts up.

On the other hand, a counter reset instruction is placed in the program so that the counter 4 is reset before it overflows. Therefore, the CPU reset signal 41 is not output.

If the program is not executed normally due to the bug operation and the counter reset instruction is not executed before the counter 4 overflows, the counter 4 outputs the CPU reset signal 41 and returns the CPU 1 to its initial state.

According to this embodiment, there is no need to consider the execution time of each CPU instruction or the time during which program execution is stopped, and only the number of program steps needs to be considered. be.

〔Effect of the invention〕

According to the present invention, since a counter is counted up every time one instruction is executed, the number of steps of the instruction, rather than the program execution time, needs to be taken into consideration when arranging the counter reset instruction, which has the effect of facilitating program creation.

Furthermore, when the CPU temporarily suspends program execution due to DMA transfer or the like, the counter stops counting up, so there is no need to take this into consideration when arranging a counter reset instruction, which has the effect of facilitating program creation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...CPU. 2... Counter reset instruction decoding means, 3...
Instruction fetch cycle decoding means, 4... Counter, 11... Address bus, 12... Data bus, 13... Control bus, 21.
・Counter reset signal line,

Claims (1)

[Claims] 1. In a watchdog timer comprising a counter reset means for decoding a CPU instruction and outputting a counter reset signal, and a counter reset by the counter reset signal, a means for decoding an instruction fetch cycle of the CPU is provided, A watchdog timer that inputs this output to a counter to count instruction fetch cycles of a CPU.