JPH02118892A - Processor - Google Patents

Abstract

PURPOSE:To simultaneously execute data transfer and data processing by successively adding +1 to a counter in the title processor according to the data transfer, executing the data processing in the processor when a counter number is a positive number, and inhibiting the data processing when the counter number is zero. CONSTITUTION:When prescribed instruction data are inputted to an instruction register 4, an instruction decoder 5 decodes the data and adds -1 to an up/down counter 1 according to the decoded result. Further, a bus control interface circuit 6 is accelerated its task of data processing until a zero output is obtained in a zero detecting circuit 2. When the value of the counter 1 goes to '0', the output of the circuit 2 comes to true, and an interruption signal is generated according to the contents of a flag register 3, starts interruption control for the circuit 6, and inhibits the data processing of the processor. In the same manner, the interruption signal generated according to the contents of the register 3 is outputted to the external part of the processor, starts interruption control for the processor from the external part, and inhibits the prescribed data processing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a microprocessor with built-in arithmetic and control circuits used in information processing devices.

Conventional technology Generally, data is transferred within a processor in a multi-processor system that does not share a bus, or data is transferred to devices on the bus that operate asynchronously, and then predetermined data processing is performed in a predetermined processor. In this case, after the task related to normal data transfer is completed, the data processing task is started for the target processor using DMA (D
direct Memory Access) device.

On the other hand, if you want to perform high-speed data processing in a predetermined processor immediately after such data transfer, in other words, DM
There is a case where it is desired to make the transfer data of the data transfer being executed at A ready for data processing at the same time as the transfer.

Examples of this include cases where it is desired to perform pipeline processing between processors in a multiprocessor at high speed, and data exchange between processors in a processor array. In such an example, it is difficult to check the transferred data, that is, to what extent the data transfer has been replaced with new data by DMA, which is especially important when synchronizing between processors due to asynchronous transfer in a multiprocessor system. It becomes a problem.

In the above example, the following methods can be used to process data in the processor immediately after asynchronous data transfer is performed for a group of data stored consecutively in memory. .

There is an FIFO (Flrst) between the storage device and the processor.
-In-First-Out) memory is arranged, and data is transferred via this. (See Figure 2)
In this case, the processor needs to perform store operations on both memory and F'IFO memory. As a second method, a data cache memory is prepared inside the processor or outside the processor, and a FIFO algorithm is used for the data cache memory to start and stop data processing tasks for the processor at the same time as data transfer. I do. However, in the first method, F'IF has a capacity corresponding to the amount of transferred data.
In the second method, complex control is required in pipeline processing etc. in order to maintain the consistency of data in the charatsuyu, that is, the unification of data in the cache memory and memory. Accompany.

Problems that the invention sought to solve In the above-mentioned system, in order to perform predetermined data processing in response to data transfer, it is necessary to perform control via a FIFO memory or a cache memory controlled by a FIFO algorithm. there were. However, in the first method, F
In the second method, it was necessary to add an IFO memory and, in the second method, a cache memory and hardware for controlling the same to the processor.

The present invention has been made to solve this problem and aims to add simple hardware to the processor, thereby making it possible to perform data processing simultaneously with data transfer.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a counter in the processor and counts the number of data that can be currently processed in the processor by sequentially adding +1 by data transfer. When is positive, data processing is performed by the processor, and when it is zero, data processing by the processor is prohibited.

Effects of the present invention With the above-described configuration, the number of data that can be processed is always indicated by a counter, so that the processor can easily recognize the transfer data that can be processed by updating the value of this counter. By updating this counter, the processor can easily update the number of data that can be processed.

Embodiment FIG. 1 is a block diagram showing an embodiment of the processor of the present invention. In FIG. 1, 1 is an up/down counter with a zero clear function, 2 is a zero detection circuit, 3 is a flag register, 4 is an instruction register, 5 is an instruction decoder, 6 is a bus control interface circuit, 7 is a general-purpose register, 8 is composed of an ALU, and an up/down counter 1 is set to + by an external bus transfer monitoring signal that monitors data transfer for each DMA transfer to the external bus interface 6.
1 count up, address register 3 to start transfer.
Store the start address of data transfer in .

Now, when predetermined instruction data is input to the instruction register 5 of the processor O, it is decoded via the instruction register 5 and the instruction decoder 4, and based on the decoding result of the instruction decoder 4,
While incrementing the up/down counter 1 by 1, the bus control interface circuit 6 is prompted to perform a data processing task until a zero output is obtained in the zero detection circuit 2.

Now, when the value of the up/down counter 1 becomes 0, the output of the zero detection circuit 2 becomes true, and an interrupt signal is generated depending on the contents of the flag register 3 indicating the zero detection result.The interrupt signal is sent to the bus control interface circuit 6. interrupt control is activated, and predetermined data processing in the processor is prohibited.

Similarly, when the value of the up/down counter 1 becomes O, the output of the zero detection circuit 2 becomes true, and depending on the contents of the flag register 3 indicating the zero detection result, the generated interrupt signal is output to the outside of the processor 0. Activates interrupt control for processor 0 and prohibits predetermined data processing in processor 0.

Effects of the Invention As described above, according to the present invention, specific data can be processed without special use of FFO memory, data cache, etc. by incorporating a relatively simple circuit into a conventional processor. A column can be made ready for data processing immediately after data transfer.

[Brief explanation of drawings]

FIG. 1 is a processor block diagram according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional multiprocessor. 1...Up/down counter with zero clear function, 2...Zero detection circuit, 3.Φφ flag register,
4. Instruction register, 5.. instruction decoder, 6..
・Bus control interface circuit, 7φ...General purpose register, 8...ALU. Name of agent: Patent attorney Shigetaka Kurino (1 person) Figure 2 External bus Figure 1

Claims (3)

[Claims] (1) An up/down counter with a zero clear function, a zero detection circuit for the up/down counter, a flag register that indicates its zero output, a bus interface circuit that controls external bus input/output, and an instruction that holds instructions. A processor comprising a register and an instruction decoder for decoding the contents of the instruction register, the processor comprising:
The down counter is incremented in accordance with the transferred data by an external bus transfer monitoring signal that monitors the external data transfer operation, and is counted down or cleared in accordance with the decoding result of the instruction decoder. processor. (2) The processor according to claim 1, wherein when the output of the zero detection circuit is true, the flag register indicating the output of the zero detection circuit outputs the output to the interrupt signal bus interface. (3) When the output of the zero detection circuit is true, an interrupt signal is output from the processor to an external signal line from a flag register indicating the output of the zero detection circuit. processor.