JP3209144B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having a plurality of maskable interrupt mask circuits and a circuit for receiving an SVI (supervisor interrupt) to selectively execute a maskable interrupt during an SVI. The present invention relates to a microprocessor having hardware capable of operating.

[0002]

2. Description of the Related Art The prior art of this type of microprocessor will be described below with reference to an example of a microprocessor disclosed in Japanese Patent Laid-Open Publication No. 1-184545. FIG. 4 shows the configuration of the interrupt prohibition circuit described in Japanese Patent Application Laid-Open No. 1-184545.

As shown in FIG. 4, a register 32 for setting whether or not to permit an interrupt during SVI, and when another interrupt occurs during SVI, generation of an interrupt mode signal until completion of execution of a return instruction of the interrupt Circuit 36 and SVI
The circuit includes an SVMODE signal that outputs “1”, an interrupt generation inhibition circuit 31 that receives an output of the register 32 and an output of the interrupt mode signal generation circuit 36, and prohibits the generation of an interrupt.

Next, the operation will be described. First, the operation when “1” is set in the register 32 will be described.

Since the output of the register 32 is "1",
The output of the two-input OR gate 33 is always "1" and R-
The output of the S flip-flop circuit 35 is always "1". At the time when the SVI does not occur, the SVMODE signal is “0”, the output of the two-input AND gate 36 is “0”, and the interrupt disabling circuit 31 does not disable the interrupt. Therefore, the general interrupt is permitted.

Here, when SVI occurs, SVMOD
The E signal becomes "1", the output of the two-input AND gate 36 becomes "1", and the interrupt disabling circuit 31 enters the interrupt disabled state.

Next, the operation when "0" is set in the register 32 will be described. Since the output of the register 32 is "0", the output of the two-input AND gate 34 is always "0", and the interrupt disable circuit 31 enters the interrupt enabled state regardless of the SVMODE signal.

At this time, the RS flip-flop 35
Even if the output Q of the register 32 changes from “1” to “0” and the output of the two-input OR gate 33 changes to “0”, the output Q holds “1”.

During the SVI, the interrupt signal INT becomes RS
When the signal is input to the flip-flop 35, the RS flip-flop 35 is reset, and the output Q thereof becomes "0", ie, the output of the two-input AND gate 36, that is, the external terminal SV.
The output of MODE becomes "0", indicating that the SVI has been interrupted.

When the interrupt is completed, the internal RETI signal (return signal from the interrupt) is output to the RS flip-flop 35.
, The output Q becomes “1” and the two-input AND
The output of the gate 36, that is, the output of the external terminal SV-MODE becomes "1", indicating to the outside that the device has entered the SVI mode again.

In the second embodiment described in the above publication, multiple interrupts are also permitted.

[0012]

Normally, a microprocessor that accepts an SVI is designed not to accept other interrupts during the SVI. Therefore, in an interrupt-dependent system or the like, an original user program is used. It has been impossible to debug or trace a user program, which is the purpose of an in-circuit emulator, without interrupting the interrupt processing operation of the CPU.

In a system or the like in which a short cycle DRAM (dynamic random access memory) is refreshed by an interrupt, etc.
There is also a possibility that adverse effects on the system, such as the inability to refresh the RAM and the inability to retain the value of the DRAM, may occur. For this reason, improvements as in the above-described prior art have been attempted.

In many systems using current microprocessors, a plurality of interrupts enter in various dependencies in a short time. In systems requiring embedded microprocessors,
In particular, its processing speed, response performance, and small mounting area (that is, reduction in power consumption cost) are often required. In this trend, in systems intended for real-time control and systems that require high response performance, interrupt dependencies are designed to be performed by hardware in order to improve interrupt response performance. Often a microprocessor is used.

[0015] However, in the prior art, the microprocessor allows interrupts by SVI in the interrupt enable mode for any interrupt, and also allows multiple interrupts to occur. That is, the number of maskable interrupts (maskable interrupts) is one, and only interrupt enable / disable can be selected.

As described above, when only uniform setting of interrupt permission / non-permission can be performed during debugging of a user program, in a system requiring processing speed, high response performance, and real-time property as described above, In addition to the indispensable interrupts that were a problem with the prior art,
Accepting a large number of unnecessary interrupts slows down the memory dump speed to the in-circuit emulator, and faithfully reproduces bugs that occur in the actual operating state of the system due to a change in the state of the user program during debugging due to a large number of interrupts. Inhibition, inhibition of real-time control, reduction of interrupt responsiveness, etc. occur.

This makes it impossible to fulfill the original purpose of faithfully debugging the user program.

Further, in a microprocessor having a structure as in the prior art, if it is intended to construct a system in which a plurality of interrupts are interrupt-dependently entered in a short time as described above, (1) the interrupt circuit of the prior art is required. It is also possible to infer from the above-mentioned prior art that a microprocessor having a plurality of insides and accepting a plurality of maskable interrupts can be inferred. Also, (2) interrupt dependency is controlled only by software, and (3) external hardware is used. There is also a means (method) for performing interrupt arbitration.

In this case, in the method of (1), the same circuit is provided in a plurality of chip circuits to increase the area, increase the manufacturing cost of the chip, increase the power consumption, and reduce the cost due to the need to customize for each system. T
AT (turnaround time) increases.

In the above method (2), the real-time controllability, response performance, and debugging performance are degraded and the user program creation TAT is increased. In the method (3), the mounting cost is increased due to an increase in mounting area and mounting components. There is a problem such as an increase in power consumption.

As described above, it has been difficult in the conventional example to construct a plurality of interrupt-dependent systems without deteriorating high processing performance, response performance, and real-time performance, and to efficiently debug them.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to specify a specific-level interrupt even during a SVI process in a microprocessor that accepts a supervisor interrupt (SVI). It is an object of the present invention to provide a microprocessor that enables efficient debugging by selectively accepting interrupts without impairing the execution environment and response performance of a user program.

[0023]

In order to achieve the above object, a microprocessor according to the present invention comprises an interrupt control circuit capable of accepting a plurality of maskable interrupt signals, and a supervisor for debugging using an in-circuit emulator or the like. And a circuit for receiving an interrupt (abbreviated as “SVI”).
Even in the maskable interrupt disabled state by I execution,
It is characterized in that it comprises circuit means for enabling unmasking of only a specific level interrupt, and means for controlling permission / non-permission of execution of a specific level maskable interrupt in SVI.

[0024]

Embodiments of the present invention will be described below. In a preferred embodiment, the microprocessor according to the present invention includes an interrupt control circuit capable of receiving a plurality of maskable interrupt signals,
In a microprocessor having a circuit for receiving I, a part of the maskable interrupt control circuit has a hardware circuit capable of performing mask release only for an interrupt of a specific level even in a maskable interrupt disabled state due to execution of SVI. , SVI, and a mask release means for selectively executing a maskable interrupt of a specific level in SVI.

In a preferred embodiment of the microprocessor of the present invention, the hardware circuit includes a system register unit for executing / non-executing / non-executing the unmasking of a specific level interrupt and setting the interrupt level; A temporary register (14 in FIG. 1) that latches the interrupt level set in the system register with the SVI signal, and a temporary register (14 in FIG. 1) that latches the interrupt level of the externally input interrupt signal with the maskable interrupt signal. 13), a comparison circuit (16 in FIG. 1) for comparing the two temporary registers and outputting a coincidence signal, and a mask control circuit for masking the internal SVI signal with the coincidence signal.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

An embodiment in which the present invention is applied to an interrupt mask circuit of a known microprocessor uPD70732 having a plurality of maskable interrupt inputs will be described below.

FIG. 1 is a diagram showing a schematic configuration of an interrupt mask circuit according to one embodiment of the present invention. Figure 2 shows the PS
FIG. 3 is a diagram showing an outline of W (program status word) and a system register ICEMR.
FIG. 3 is a diagram illustrating a state table of a mask circuit.

Referring to FIG. 1, the microprocessor 1 of the present embodiment includes a supervisor interrupt (privileged interrupt, hereinafter abbreviated as "SVI") provided for debugging, which is an interrupt for the purpose of debugging that is not disclosed to the user. A request status external input terminal BRKINT and a program status word register (hereinafter referred to as “PSW”) 11 storing a flag group indicating the result of instruction execution and the state of the processor itself (the above configuration is present in the existing product uPD70732). ), And a newly provided interrupt enable level flag MI (Mask Interrupt Level).
l) and the mask release mode flag ME (Mask Ena)
ble, “0” unmasking OFF, “1” unmasking ON), receives the values of the MI and ME bits of the system register ICEM12, and masks the output from the NP (NMI Pending) bit of the PSW 11 It has a maskable interrupt enable circuit 6 having a built-in SVI mask circuit 7.

In the SVI mask circuit 7, the values of the temporary register 13 whose initial value after reset is 0, the temporary register 14 whose initial value after reset is F, and the values of the temporary registers 13 and 14 are represented by n , L, and a comparison circuit 16 that outputs “1” if n = 1.

The ICEMR 12 and the like may use an undefined field of an existing register.

First, ME (Mask) of ICEMR12
When the “Enable” bit is set to “0”, the output of the two-input NAND 17 is always “1”.

In the microprocessor 1 of this embodiment, up to 16 interrupts are permitted. When the interrupt signal INT is input to the interrupt mask circuit 6 from the external input terminal 22, the value m of the interrupt enable level flag I3-I0 of the PSW 11 in the system register unit and the interrupt level input from the external input terminal 21 The comparison circuit 15 compares the interruption level n of the signal INTV (3-0) with the comparison circuit 15. If n ≧ m, the comparison circuit 15 outputs a value “1” indicating interruption permission.

While the comparison circuit 15 is outputting "1", other interrupt conditions (status flags NP, E
When P, AE, and ID are all "0"), the interrupt valid signal INTvalid becomes "1" (that is, active), and the maskable interrupt process is started.

Here, NP (NMI Pending)
Is a flag indicating that non-maskable interrupt processing is in progress, and EP (Exception Pending) is
Flag indicating that exception / trap / interrupt processing is in progress, AE (Address Trap Enable)
Is a flag indicating that the address trap function is being activated, ID (Interrupt Disable)
Is a flag indicating whether or not an external interrupt request is accepted (see FIG. 2).

If any of these flags is "1", the interrupt is masked and not accepted.

BRKI input from the external input terminal 23
When the NT (-) signal becomes active and SVI processing is being performed, the INTvalid signal becomes inactive because the NP bit is set to "1", and maskable interrupts are not permitted.

Next, in the ME bit of the ICEMR12,
A case where “1” is set will be described. First, ICE
The value l of the interrupt level for which interruption is to be permitted even during SVI is set to the MI bit in MR12.

Since the initial output of the comparison circuit 16 is "0", the external input signal BRKINT (-) indicating the SVI request
Until is activated, the output of the two-input NAND 17 is always "1".

Therefore, if EP, ID, and AE are each "0" and the interrupt level is higher than the permission level, the maskable interrupt is accepted.

When an SVI request occurs and BRKINT
When the (-) signal becomes active, the value l of the MI bit of the ICEMR 12 is set in the temporary register 14, but at this time, the output of the comparison circuit 16 is "0".
Remains.

When the SVI processing is completed, the internal return instruction BRKRET signal from the SVI is sent to the temporary register 1
3 and 14 are reset.

When the maskable interrupt request signal INT becomes active during SVI, the temporary register 1
3, the value n of the interrupt request level is set, and the comparison circuit 16 compares the value n of the temporary register 13 with the value 1 of the temporary register 14.

If n ≠ 1, the output of the comparison circuit 16 is “0”
The maskable interrupt is not enabled.
If n = 1, the output of the comparison circuit 16 becomes “1” and 2
The output of the input NAND 17 becomes “0”, masks the NP flag, cancels the interrupt inhibition by SVI, and if other conditions are met, the INTvalid signal becomes “1” and a maskable interrupt can be executed. become.

The embodiment of the present invention has been described above. Here, only one level of interrupt is enabled, but an arbitrary number of interrupts of any level can be allowed by setting a plurality of interrupt enable level flags in the MI bit.

[0046]

As described above, according to the present invention,
Since a maskable interrupt of a specific level can be selectively executed by hardware at the time of SVI, the original program expected by the user program can be performed without deteriorating real-time controllability and responsiveness particularly in an interrupt-dependent system. This has the effect of enabling the system to be debugged while minimizing the hindrance of operation.

According to the present invention, when constructing a system, the processing speed can be easily, reliably and flexibly reduced in a small area of a chip without imposing a burden on a user program or external hardware as compared with the conventional method. -High response performance-Has the advantage that an interrupt-dependent system that performs a large number of interrupt processes without impairing the real-time property can be constructed.

That is, suppression of chip and system area increase, reduction of cost and power consumption, reduction of user program creation TAT, high response performance and processing speed and real-time controllability, and reproduction of operation faithful to the operation state of the system.
Debugging can be performed simultaneously.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 shows PSW and ICEMR in one embodiment of the present invention.
FIG.

FIG. 3 is a state table illustrating an embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating a conventional technique.

[Explanation of symbols]

 1, 2 Microprocessor 3 System register unit 4 Other unit 5 Interrupt mask circuit 6 SVI mask circuit 11 Program status register (PSW) 12 System register (ICEMR) 13, 14 Temporary register 15, 16 Comparison circuit 17 , 18 2-input NAND 31 interrupt prohibition circuit 32 register 33 2-input OR 34, 36 2-input AND 35 RS flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/28 G06F 9/46 311 G06F 11/22 340

Claims (3)

(57) [Claims] A microprocessor configured to receive a plurality of maskable interrupt signals and to receive a supervisor interrupt (abbreviated as "SVI") for debugging by an in-circuit emulator or the like. Even when maskable interrupts are disabled, the mask is released for interrupts of a specific level
A microprocessor comprising circuit means, whereby the maskable interrupt of the specific level can be selectively received even during SVI processing. An interrupt control circuit for receiving a plurality of maskable interrupt signals;
A circuit that accepts a supervisor interrupt (abbreviated as “SVI”) for the purpose of debugging by an emulator or the like. A part of the maskable interrupt control circuit includes a specific level even when maskable interrupts are disabled by SVI execution. A microprocessor capable of performing mask release only for the interrupt of (i), and a means for controlling permission / non-permission of execution of a maskable interrupt of a specific level in SVI. 3. The method according to claim 1, wherein the unmasking circuit means executes / non-executes / unexecutes masking for a specific level interrupt.
A system register for setting an interrupt level thereof, a first temporary register for latching the interrupt level set by the system register with an SVI signal, and a maskable interrupt signal for an interrupt level of an externally input interrupt signal. The second temporary latch
A register, a comparison circuit that compares the first and second temporary registers and outputs a match signal, and a mask control circuit that masks an internal SVI signal with the match signal from the comparison circuit. The microprocessor of claim 1, wherein: