JP3449812B2 - Control electronics - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control electronic device having a control program built therein, and more particularly to a control electronic device configured to facilitate debugging of the control program. .

[0002]

2. Description of the Related Art Generally, when a control electronic device such as a microcomputer is mounted on a device to be controlled to perform control, it is necessary to perform debugging including hardware when developing a control program for this electronic device. There is. As a method for enabling debugging including such hardware, there has been a conventional In-Circuit Emulator.
Although a logic analyzer (hereinafter referred to as ICE) or the like is used, normally, when debugging is performed using ICE, the CPU in the electronic device is removed and I
An evaluation chip that can be connected to a CE is manufactured, and an IC is mounted in a state in which the evaluation chip is mounted on the target control target device.
By connecting with E, processing for debugging such as temporary stop of application program, reference / setting of memory, or disassembly is executed.

[0003]

As described above, conventionally, there has been a problem that an evaluation chip must be specially manufactured in order to perform debugging including hardware by using ICE. For a control target device in which a control electronic device has been incorporated, the control electronic device must be removed and replaced with an evaluation chip or the like.
It was not possible to debug using CE.

Normally, when performing operations such as memory reference / setting using the ICE, it is necessary to suspend the emulation of the program. However, depending on the control device, the suspension of the emulation causes a problem. Some of them are not easy to suspend the execution of the program, which is inconvenient for the debugging process.

[0005]

According to the present invention, a central processing means, a fixed storage means for storing an application program and a debugging program for executing a debugging process, and a predetermined address selected by an operator are stored. The first storage means, the second storage means, the comparator for comparing the execution address of the central processing means with the predetermined address stored in the first storage means, and the comparison output of the comparator are input. When there is a portion to be patch-corrected in the application program stored in the fixed storage means due to the presence of a bug or the like, the start address of the patch-corrected portion is stored in the first storage means. At the same time, instead of this patch correction part, the patch correction program stored in a predetermined location in the device to be executed is executed. The patch start data for starting the patch correction operation is stored in the second storage means, and when the execution address matches the correction address, the access of the central processing means is made based on the coincidence output of the comparator. A control electronic device for executing the patch correction program by switching from fixed storage means to the second storage means, and executing the debug program when a break request is received from an external host computer during debugging. The break address is stored in the first storage means, the debug start data for starting the debug process is stored in the second storage means, the break release flag is turned off, and the switching circuit is Based on the match output of the comparator indicating that the execution address matches the break address Switching the access of the central processing means from the fixed storage means to the second storage means to put the application program in a break state for debug processing, and interrupting the restart program when a restart command is issued from the host computer. Then, the value of the break release flag is inverted and the execution of the application program is restarted.

Here, it is preferable that the debug start data is a jump instruction to a debug program.

[0007]

The processing for debugging the application program installed in the control electronic device is performed by the control electronic device itself. The operator can arbitrarily specify the start address for the debug processing. Even during the debug processing operation, the control electronic device can accept the interrupt processing.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various microcomputers are currently used as control electronic devices, and among them, an embodiment in which the present invention is applied to a known one-chip microcomputer capable of patch correction is known. explain.

An example of the configuration of such a one-chip microcomputer is shown in FIG.
Shown in. First, the patch correction in this microcomputer will be briefly described below. Details of the patch correction operation in such a microcomputer are described in, for example, Japanese Patent Laid-Open No. 6-2
No. 22917.

In the configuration shown in FIG. 1, when there is a portion to be patch-corrected in the application program stored in the ROM 5 due to the presence of a bug or the like, the start address of the patch-corrected portion is stored in the correction address register 2 and A patch correction program to be executed instead of this patch correction portion is stored in the RAM 6. Further, a preprocessing program for performing various kinds of preprocessing required when switching the program execution in the CPU 1 from the application program to the patch correction program is stored in a specific area in the ROM 5, and further,
The correction data register 4 stores a table call instruction for shifting the operation of the CPU to the patch correction operation.

In the control operation by the microcomputer, when the patch correction is executed based on the patch correction data stored in the registers 2 and 4 and the RAM 6 and the ROM 5, the control flag latch 3 is previously set to the value "1". The flag of is stored.

Patch correction in the microcomputer configured as described above is performed as follows. That is, when the execution of the application program by the CPU 1 progresses and its execution address matches the correction address, the output of the comparator 7 becomes the value "1" and the output signal of the AND gate 8 becomes active (the value "1"). This signal is supplied to the correction data register 4 and the inverted inactive signal is supplied to the ROM 5. This allows
The CPU 1 will accept the table call instruction in the correction data register instead of the command of the application program in the ROM 5. Since the start address of the preprocessing program is called by this table call instruction, execution of this preprocessing program is started, and after that, when the patch correction program in the RAM 6 is entered and the execution of this program is completed, the ROM 5 Performs the operation to return to the next address of the patch correction part of the application program.

In the microcomputer shown in FIG. 1, the patch correction is executed as described above.
In this microcomputer, various operations necessary for debugging, for example, execution of the application program is interrupted at a desired address, execution of the application program is restarted from this interrupted address, or registers and A program for executing operations such as memory reference / setting, etc. (hereinafter,
(Which is called a debug monitor) is installed in the microcomputer together with the application program in advance.
The debugging process can be performed without using CE.

The commands for executing these debug monitors are configured to be given to the microcomputer from an external host computer using a serial or parallel communication path. This communication path may be either occupied by the debug monitor or dividedly used with the application program. Next, as an example of the debug monitor,
Interruption of application program execution (break)
2 and FIG.
Will be described with reference to.

FIG. 2 shows a program for interrupting the execution of the application program. When the microcomputer receives a break request including break address data from the host side, it executes the program shown in [1] of this figure. At step S2 and step S3, the data necessary for executing the interruption operation are stored in the correction address register, the correction data register, etc., and then the process returns to the original application program. When the execution of the application program progresses and the execution address matches the break address, the address jumps to the address called by the break table call instruction. On the other hand, since the program shown in [2] of this figure is written after this called address, the CPU executes step S4 of this program to perform the save process, and then the break release flag. The loop of step S5 is repeated until is turned on to enter the suspended state.

Here, the break cancellation flag is turned on only when a restart command is issued from the host side, and the program executed based on this restart command is as shown in FIG. That is, when the restart command is issued, the values of the control flag and the break release flag are inverted by the execution of this program, and then the process returns to step S5 of [2] in FIG. After returning to the state of, jump to the break address and resume the execution of the application program. Each of the programs shown in FIGS. 2 and 3 is R
It can be stored in the OM5. In these suspend / resume operations, the PSW and register values are saved and
Since the restoration process is performed, there is no influence of interruption when resuming the application program.

As described above, in order to switch the program execution by the CPU among the application program, the suspending program, and the resuming program in response to a command from the host side, the application program, FIG. The interrupt program consisting of [1] and [2] and the resume program of FIG. 3 are given different priorities as one task respectively, and these tasks are switched and executed in accordance with a command from the host side. Task-based OS (Operation Sy)
It can be easily realized by adopting a system). Also, the OS
In the case of a microcomputer that did not use, for example, insert the program [1] of FIG. 2 into the application program, and execute the step S2 of the inserted program when the interruption command is received. This can be realized by shifting to the program of [2] of FIG. 2 by the break address on the application program and by executing the restart program of FIG. 3 as an interrupt program.

In the configuration shown in FIG. 1, since the patch correction and debug processing share the components 2 to 4 and 7 to 9, it is not possible to perform the debug processing on the patch correction program. Although it is not possible, if the same components as 2-4 and 7-9 above are installed in another set in the microcomputer and each set is used only for patch modification and debug processing, the program related to patch modification can also be debugged. Processing can be performed.

In the embodiment described above, the table call instruction stored in the modified data register is used to jump to the program for interruption.
Instead, when a suspend command is accepted, a jump instruction for suspending operation is written in the correction data register, and the jump destination address of this jump instruction is provided with a table for the table call instruction. It is also possible to use a microcomputer defined as being stored in a specific register different from the memory in which it is stored.

The structure of such a microcomputer is shown in FIG.
In the configuration of this figure, the register 12 is a variable jump destination address register in which the address of the jump destination for the suspend operation is stored, and when the suspend command is input from the host side, the program of [1] in FIG. Instead, the program shown in FIG. 5 is executed. Then, in step S21 of this program, the jump destination address is written in the register 12. Note that the same program as in [2] of FIG. 2 is stored after this jump destination address, and the restart operation is also executed according to the same program as in FIG.

In addition, as a simpler method for interrupting the execution of the application program to the microcomputer, an infinite loop is executed at the break address in the correction data register 4 in FIG. 1 when the interrupt command is received. An instruction to be performed (a specific example of such an instruction may be, for example, an instruction to jump to a break address) may be written. Program of interruption operation when adopting such a method,
An example of the program for the restart operation is shown in [1] and [2] of FIG. However, in this example, as is clear from this figure, since the PSW and register values are not saved / restored, the internal state of the CPU is not saved during the interruption operation. If the method of executing an infinite loop with a break address is used and the sharing of the patch correction circuit is not considered, the correction data register 4 may be configured by a ROM.

Although the interrupt / resume debug monitor has been described above, in addition to this, operations such as memory reference / setting and disassembly can be executed by incorporating the debug monitor in the microcomputer. As an example, FIG. 7 shows the configuration of a debug monitor for disassembly. In this figure, when the microcomputer receives a disassemble request including disassemble start address data from the host side, steps S15 to S17 are executed to display the disassembled mnemonic language on the host side. The microcomputer may be configured to transmit the program code before being converted to the mnemonic to the host side, and the conversion operation to the mnemonic may be executed on the host side. In addition, a debug monitor for this disassembly etc. is also stored in advance in the ROM.
In this disassembly operation, the break address on the application program is not particularly designated at the time of starting the disassembly operation.

Although FIGS. 1 and 4 have been described on the premise that the microcomputer is a patch-correctable microcomputer,
It does not necessarily have to be a microcomputer that executes patch correction, but in short, 2-4 and 7-9 shown in these figures are necessary.
It is sufficient if the microcomputer has components such as. However,
The comparator 7 is not limited to such a hardware configuration and may be replaced with software.

[0024]

According to the present invention, without using ICE,
Since the program can be debugged including the hardware while the microcomputer is still mounted in the control device, it is not necessary to prepare a special evaluation chip for debugging. Since the microcomputer itself performs the debug operation by executing the debug program incorporated therein, unlike the case where the ICE is used, the microcomputer main body is in the operating state even during the debug processing operation. Various interrupt processes can be accepted even during the debug process operation. Therefore, it is easy to operate when performing various processes for debugging.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a flow for an interruption operation in the embodiment.

FIG. 3 is a diagram showing a flow for a restart operation in the embodiment.

FIG. 4 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a diagram showing a flow for middle-stage operation in another embodiment.

FIG. 6 is a diagram showing a flow for a middle stage operation and a restart operation in yet another embodiment of the present invention.

FIG. 7 is a diagram showing a flow for a disassemble operation in the embodiment of the present invention.

[Explanation of symbols]

1 CPU, 2 modified address register, 3 control flag latch, 4 modified data register, 5 RO
M, 6 RAM, 7 comparator, 12 jump destination address register,

Front Page Continuation (72) Inventor Naoki Murayama 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Iwa Yamamoto 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Shares In-company (56) Reference JP-A-6-222917 (JP, A) JP-A-5-298462 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/22, 11/28

Claims (2)

(57) [Claims] 1. Central processing means, fixed storage means for storing an application program and a debugging program for executing debug processing, first storage means for storing a predetermined address selected by an operator, and 2 storage means, a comparator for comparing the execution address of the central processing means with a predetermined address stored in the first storage means, and a switching circuit to which the comparison output of the comparator is input, When there is a portion in the application program stored in the fixed storage means to be patch-corrected due to the existence of the patch, the start address of the patch-corrected portion is stored in the first storage means and the patch-corrected portion is replaced. Start patch correction operation that executes the patch correction program stored in the specified location in the device to be executed The patch starting data for storing the data is stored in the second storage means, and when the execution address matches the correction address, the access of the central processing means is accessed from the fixed storage means based on the coincidence output of the comparator. An electronic control device for switching to the second storage means to execute the patch correction program, wherein an external host computer is used for debugging.
When receiving the rake request, by executing the debug program stores the break address to the first memory means, stores the debug initiation data for initiating debugging process in the second storage means, Bray
And the switching circuit turns off the access of the central processing means from the fixed storage means based on the coincidence output of the comparator indicating that the execution address coincides with the break address. Switch to the means and put the application program in the break state
Performs debug processing and restarts from the host computer
Interrupt the restart program when a command is issued
Run as a ram and reset the value of the break release flag.
Rolling and control electronics, characterized that you resume execution of the application program. 2. The control electronic device according to claim 1, wherein the debug start data is a jump instruction to a debug program.