JPS58161046A - Interruption controlling circuit - Google Patents

Abstract

PURPOSE:To prevent the runaway of a program, by generating a power-on reset signal to return the program to the initial state when a vector address generation start signal is issued or an interruption request disappears erroneously because of a malfunction. CONSTITUTION:When an interruption is caused from a timer, a terminal, or the like, an interruption start signal Pi is outputted from timers 1 and 2 and INTs 1 and 2 to an arithmetic logical unit 3, and saving of contents of registers 4a- 4d to a memory 7 is started after an executing instuction is terminated. If the interruption is started by the malfunction of a timer counter or the like to output a vector address generation start signal Ps or to lose the interruption request, the state of no interruption signal from timers 1 and 2 or INTs 1 and 2 to a vector address generating part 10 is set. Then, a signal from a power-on reset terminal RES is inputted to the generating part 10 through a NOR gate 8 and an OR gate 9, and a specific vector address is generated from the generating part 10 and is loaded to a program counter 4d, and registers 4a-4d are set to the initial state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vector address type interrupt control circuit, and in particular to an interrupt control circuit VCIll that performs a power-on reset when a vector address generation start signal is generated by mistake. .

In a micro combiator to which interrupt control using the vector address method is applied, when the combiator receives an external interrupt request from a terminal device, a timer interrupt request from a timer counter, or an internal interrupt request from software, 1 A preset vector address (indirectly specified address) is generated according to the contents of the interrupt request. Then, the contents stored in the memory area specified by the vector address (the address indicating the address where the first instruction of the interrupt program is stored) are transferred to the program counter. The instructions stored in the area are read into the instruction register, the program jumps to the interrupt routine, and the first instruction is read in depth.

However, in the vector addressing method of interrupt control, an interrupt request signal may be output by mistake from a timer counter, etc., or the interrupt request may disappear between the time the interrupt request is issued and the vector address is generated5. Sometimes.

Traditional! Ikroproset? (hereinafter referred to as CPLj), in such a case, when the first interrupt request signal comes in, it continues the instruction in progress to the end and then starts responding to the interrupt request. Regardless of the contents of one interrupt request, the index register or program counter is first read.

The contents of the code register are saved in the stack area of memory (RAM).

The registers are saved before the vector address is generated, and after the save is completed, the vector address is generated and branched to the interrupt program.

Therefore, if a generation start signal is output to the vector address generation section due to a malfunction of a timer counter, etc., or if an interrupt request disappears after receiving an interrupt request signal but before a vector address is generated, There was a risk that a program that should not be executed might be executed or the program might run out of control.

Therefore, in the case where a vector address generation start signal is erroneously issued due to a malfunction of the timer counter, or when an interrupt request disappears immediately before vector address generation, the power-on reset signal is generated by hardware. The purpose of this is to return the program to its initial state by causing the program to return to its initial state, thereby eliminating the negative impact on the system.

This 1iIII# will be explained below based on the figure INK.

The stripe 1s shows an example of the interrupt control path a according to the present WRIIC.
Timer interrupt notes and lN from tie 11 and timer 2
An external sin interrupt signal from Tl, NTl or an interrupt signal section by software is inputted. In addition, ties-fl, 2 and lNTl, 2 are
When an interrupt request is received, the calculations within the CPU are executed.
It is configured to output interrupt compensation -1lPl for 1'C.

Arithmetic logic Sankyo knit 3 is Aki Todoroki-Gorata 4m.

The index register 4b, condition code register 4c, and program counter 4 (II) registers are connected to the memory 7 via the address bus 5 and the data bus.The memory 7 is a ROM (read-only). memory) and RAM (random 0 access/
memory).

Inside the ROM, an address indicating a storage potential of a corresponding interrupt program is stored in an area designated by a vector address generated from the vector address generating section 10 according to the contents of an interrupt request. . Further, the first instruction of one interrupt program is stored in the area indicated by the above address in the memory 7.

The various interrupt signals supplied from the timers 1, 2 and lNTl, 2 to the vector address input section 1m are as follows:
The output of the NOR gate 8 is also input to one input terminal of the OR gate 9. OR
A signal from the J5 power-on reset terminal RE8 is input to the other input terminal of the gate 9, and the oaj-tos
The output of Ill OK is supplied to the vector address generator Ill OK. Furthermore, the vector address generation section 10 is configured to be supplied with the vector address generation start signal Ps output from the arithmetic logic unit 3. Is the vector address generation 111G the above Toushi Confucian code? When a request is received, a vector address corresponding to the contents of the interrupt request is generated based on the interrupt signal from -ima 1, 2 or lNTl, 2. When a plurality of interrupts No. 1 are received by the vector address generator 11g10, the vector address corresponding to the interrupt request with the highest priority is generated.

Next, the operation of the above interrupt control circuit will be explained.

When there is an interrupt request from a timer, an end device, etc., an interrupt signal Pi is output from the timer 1.2 or tIs'r1, 2 to the arithmetic logic unit 3.

Then, after the instruction in depth is completed, register 1m1
Evacuation of 4a to 4d is started. Registers 4a to 4-
The saving is performed by storing the contents of the stack area k and registers in the memory (RAM) 7 indicated by the stack pointer.

When the saving of the registers is completed, a vector address generation start signal Ps is output from the arithmetic logic unit 3 to the vector address generation III Ok.

If at least one interrupt signal from tie 11.2 or lNT 1.2 is input when the 1M signal Ps is input, the vector address generator 1110 generates a vector corresponding to the interrupt request with the highest priority. Generate an address.

This vector address is loaded into a program counter and supplied to a memory (ROM) 7 via an address bus 5. A 16-bit address stored in the area designated by this vector address is read from the ROM via the data bus 6 and entered into the program counter 4d.

Next, this address is again output to the register 7 via the address register 5, and the instruction stored at the address specified by this address is retrieved and placed in the instruction register. is the first instruction of the desired interrupt program, and when this instruction is executed, the program counter 44 is incremented.
Then the interrupt program starts running.

At the end of the interrupt processing routine, a return interwoven instruction is executed. By this command.

The contents saved in the stack area of the memory (hada AM) are restored to the original registers Ig4a-44.

As a result, the last address before one interrupt is stored in the program counter 44, so that the original program program can be continued.

By the way, the above operation is an operation when at least one interrupt signal is input to the vector address generation 6110 when a vector address is generated.

In this case, since at least one of the inputs of NOR gate 1 is at high level, the output of NOR gate 8 is at low level.

However, if the timer counter malfunctions and an interrupt is started and the vector address death start signal P is output, or if the interrupt request disappears after the interrupt WR is started but before the vector address is generated, when the vector address is generated, Condition where there is no interrupt signal input to the vector address generation unit 10 from ties 11, 2 or lNT 1.2 II#! c.

However, when all the interrupt signals from timers 1 and 2 or lNT1.2 disappear, all the inputs of the NOR gate 80 become low level, and the output is changed to high level. This high level signal from NOR gate 8 is input to vector address generation section 10 via OR gate 9.

Therefore, the vector address generation section 10 is brought into a state where the power-on reset signal is input.

Accordingly, the vector address generation section 10 generates a vector address unique to power-on reset, such as an address for an initialization routine. As a result, the vector address of is loaded into the program counter 4d,
Registers 11141-4d are now set to their initial states.

As explained above, this invention prevents the malfunction of a timer counter, etc., from outputting only a vector address generation start signal, or when an interrupt request is generated before a vector address is generated after Combi Island-Yu accepts the interrupt request. In such a case, a power-on reset signal is supplied to the vector address generation Ii. This restores all data to its initial state and restarts the program. This prevents programs from running out of control and adversely affecting the system, thereby improving the reliability of the system.

[Brief explanation of the drawing]

11111! FIG. 1 is a circuit configuration diagram showing an embodiment of an interrupt control circuit according to the present invention. 3...Engin g logic enit, 5...Address bus, 6
...Data bus, Ps...Vector address generation start signal.

Claims (1)

[Claims] When the microprocessor accepts an interrupt request, registers are automatically saved, a vector address corresponding to the interrupt request is generated, and the desired interrupt program is executed. In microcombi routers, even if an interrupt occurs due to a malfunction and a vector address generation start signal is input to the vector address generator, if there is no interrupt signal, a vector address for power-on reset is generated. An interrupt control circuit characterized by: