JPH03255528A - Microprogram controller - Google Patents

Abstract

PURPOSE:To suppress the increase of the hardware quantity and to execute the speed control of a microprogram by one microprogram by setting the data corresponding to necessity of two flip-flops and one register from an external device. CONSTITUTION:The controller is provided with a first and a second flip-flops 3, 4 to which a state value can be set from an external device, registers 1, 2 to which a micro-instruction containing a next precedent control processing start instruction and a next instruction/interruption processing execution start instruction can be set from the external device, and control circuits 5 - 7. Accordingly, this controller works as a circuit for changing the kind of a micro- instruction for executing the next instruction/interruption processing execution start instruction for executing the speed control of a microprogram and a speed control circuit and a debug circuit for checking whether an interference is generated between each instruction/interruption processing execution control microprogram or not. In such a way, the hardware quantity decreases, the design manhour decreases, the reliability is improved, and the device cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to a microprogram control device having a speed regulating function and a debugging function for a microprogram.

[Conventional technology]

Conventionally, this type of microprogram control device prepares multiple microinstructions for instructing the start of execution of the next instruction/interrupt processing in order to control the speed of the microprogram, and depending on the type of these microinstructions, the execution of the next instruction/interrupt processing is started. Control was such as to change the number of machine cycles until an instruction is actually given to the arithmetic execution unit. Furthermore, a debug circuit for checking whether interference has occurred between the instruction/interrupt processing execution control microprograms is completely separate from the speed regulating circuit of the microprograms.

[Problem to be solved by the invention]

In the conventional microprogram control device described above, in order to control the speed of a microprogram, it is necessary to change the type of microinstruction that instructs the start of execution of the next instruction/interrupt process. The disadvantage is that microprograms must be prepared and microprogram management must be performed multiple times, and there is no interference between the microprogram's speed regulating circuit and each instruction/interrupt processing execution control microprogram. Since it has a completely separate debug circuit for checking, it has the disadvantage that it requires a large amount of hardware, leading to an increase in design man-hours, a decrease in reliability, and a rise in equipment costs.

[Means to solve the problem]

The microprogram control device of the present invention includes first and second flip-flops whose state values can be set separately from an external device, and a next preceding control device that instructs the preceding control device to start the preceding control process to be executed next. a register in which an external device can set a microinstruction including a processing start instruction and a next instruction/interrupt processing execution start instruction for instructing an arithmetic execution unit to start the next instruction to be executed or interrupt processing; When the state value held by the register is set, the next preceding control processing start instruction held in the register is regarded as a true next preceding control processing start instruction, the other next preceding control processing start instructions are invalidated, and the above-mentioned next preceding control processing start instruction is invalidated. When the state value held by the first flip-flop is in the reset state, the first control circuit validates all next preceding control processing start instructions, and the state value held by the second flip-flop is in the set state. Then, the next instruction/interrupt processing execution start instruction held in the register is regarded as the true next instruction/interrupt processing execution start instruction, other next instruction/interrupt processing execution start instructions are invalidated, and the second instruction/interrupt processing execution start instruction is invalidated. When the state value held by the flip-flop of When the control processing start instruction or the next instruction/interrupt processing execution start instruction is invalidated, the microinstruction held in the register is executed after the last step of the currently executing instruction/interrupt processing execution control microphrogram is executed. and a third control circuit for controlling the device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

First, in the microprogram of this embodiment, it is assumed that an instruction to start executing the next instruction/interrupt process is issued at the final step of the process.

Register 1 is a register that holds a microinstruction to be executed that is supplied from a signal line 100, and register 2 is a register that holds a microinstruction that is set via a signal line 200 by an external device by so-called scan control. Flip-flops 3 and 4 are flip-flops that hold state values set via signal lines 201 and 202, respectively, by so-called scan control from an external device.

In the control circuit 5, the flip-flop 3 has a state value logic “1”.
is held, even if the next preceding control processing start instruction is held in register 1, the signal line 108 is used to invalidate this instruction, and the signal line 110 is used to invalidate this instruction. This is a control circuit that notifies the control circuit and does not perform any operation when the flip-flop 3 holds the state value logic "0". When the flip-flop 4 holds the state value logic "1", the control circuit 6 uses the signal line 109 to invalidate the next instruction/interrupt processing execution start instruction even if the next instruction/interrupt processing execution start instruction is held in the register 1. and notifies via signal line 111 that this instruction has been invalidated,
When the flip-flop 4 holds the state value logic "0", it is a control circuit that notifies via the signal line 111 that the final step of one process of the microprogram has been executed. Further, when the control circuit 7 receives a notification via the signal line 110 that the instruction to start the next preceding control process is invalidated, the instruction to start executing the next instruction/interrupt process is invalidated via the signal line 1.11. In the next machine cycle after receiving a notification or a notification that the final step of one processing of a miterable program has been executed, signal line 1 is sent to indicate that the microinstruction held in register 2 is the microinstruction that should truly be executed.
Output to 12.

Next, the control circuit 6 will be further described. Signal line 113・
The control circuits 5 and 6 instruct the control circuits 5 and 6 not to invalidate the next preceding control processing start instruction and the next instruction/interrupt processing execution start instruction in the next machine cycle via the signal line 114.
When receiving a notification that the next instruction/interrupt processing execution start instruction has been disabled via the 112, signal line 113
This is a control circuit that instructs the control circuits 5 and 6 via 114 not to invalidate the next preceding control processing start instruction and the next instruction/interrupt processing execution start instruction in the next machine cycle. The selector 8 is a selector that selects the register 1 unless it is instructed via the signal line 112 that the microinstruction held in the register 2 is the microinstruction to be truly executed.

Next, the operation of this embodiment will be explained.

It is now assumed that both flip-flops 3 and 4 are set to logic "1", and the register 2 is set with a microinstruction including an instruction to start the next preceding control process and an instruction to start executing the next instruction/interrupt process. In addition, register 1 holds a microinstruction including an instruction to start the next preceding control process.
Assume that a microinstruction to be executed next, including a next instruction/interrupt processing execution start instruction, is supplied to the register l via the signal line 100 in the next machine cycle.

The microinstruction held in register 1 is supplied to selector 8 via signal line 101, but this microinstruction is one step in the middle of processing, and in this case, it is the output of register 2 from signal line 112. Since no instruction to select signal line 104 has been issued, selector 8 outputs the output of register 1 to signal line 107. At this time, the control circuit 5 is notified via the signal line 102 that the next preceding control processing start instruction exists in the register 1, and the state value logic "1" of the flip-flop 3 is transmitted to the control circuit 5 via the signal line 105. , the control circuit 5 invalidates the next preceding control process start instruction via the signal line 108 and
10, the control circuit 7 is notified that the instruction to start the next preceding control process has been invalidated. Thereby, the control circuit 7 stores this notification. Since the next instruction/interrupt processing start instruction is not present in the register 1, the control circuit 6 does not perform any operation.

In the next machine cycle, register 1 holds a microinstruction including a next instruction/interrupt processing start instruction. The microinstruction held in register l is supplied to selector 8 via signal line 101, but as in the previous machine cycle, an instruction to select signal line 104, which is the output of register 2, is issued from signal line 112. Therefore, the selector 8 outputs the output of the register 1 to the signal line 107. At this time, the control circuit 6 is notified via the signal line 101 that the next instruction/interrupt processing execution start instruction exists in the register 1, and the state value logic "1" of the flip-flop 4 is controlled via the signal line 106. Since the control circuit 6 has been notified, the control circuit 6 invalidates the next instruction/interrupt processing execution start instruction via the signal line 109 and also invalidates the next instruction/interrupt processing execution start instruction via the signal line 111. The control circuit 7 is notified of this fact. As a result, the control circuit 7 instructs the signal line 112 to select the signal line 104, which is the output of the register 2, in the next machine cycle, and also instructs the signal line 110, 111
Instructs the control circuits 5 and 6 not to invalidate the next preceding control processing start instruction and the next instruction/interrupt processing execution start instruction in the next machine cycle. The control circuit 5 does not perform any operation because there is no instruction to start the next preceding control process in the register 1.

In the next machine cycle, the selector 8 selects the signal line 104 which is the output of the register 2 via the signal line 112, and outputs the output of the register 2 to the signal line 107 as a microinstruction to be truly executed. As a result, the microinstructions including the next preceding control processing start instruction and the next instruction/interrupt processing execution start instruction held in the register 2 are executed, and the execution of the next optical row control processing and the next instruction/interrupt processing is started.

This means that the next preceding control processing start instruction was issued two machine cycles later, and the next instruction/interrupt processing execution start instruction was issued one machine cycle later.
The next instruction after interrupt processing/Interrupt processing starts at step 2.
This results in a machine cycle delay, indicating that the performance of the microprogram can be changed without changing the microprogram.

In addition, when the microprogram and advance control device issue a memory request to the microinstruction set in register 2 in addition to an instruction to start next advance control processing and an instruction to start execution of next instruction/interrupt processing, it is registered in the memory request buffer and a memory request reply is sent. When the microprogram receives the corresponding registration request from the memory request buffer, by setting an instruction to wait until the request in the memory request buffer becomes empty, each instruction/interrupt process can be executed. If the control microprogram terminates without receiving the memory request it issued, it will continue to wait at this step, so it can be used as a debug circuit because it can detect abnormalities in the microprogram by so-called stall monitoring. .

As one operation of this embodiment, the case where both the flip-flops 3 and 4 are at logic "1" has been described, but other cases will also be briefly described.

Flip-flop 3 is logic “O” and flip-flop 4
If the logic is "1", if a microinstruction containing the next instruction/interrupt processing execution start instruction is set in register 2, one machine cycle in the case where both flip-flops 3 and 4 are logic "1". The instruction to start the next preceding control process is not invalidated in the second machine cycle and is issued as is, and in the second machine cycle, the same operation as when flip-flops 3 and 4 are both logic "1" is performed, and in the third machine cycle, the next instruction is issued. The microinstruction including the interrupt processing execution start instruction is executed as the microinstruction that should actually be executed. As a result, the start of the next instruction/interrupt process after this instruction/interrupt process will be delayed by one machine cycle.

Flip-flop 3 is logic “1” and flip-flop 4
When the logic is "O", by setting a microinstruction including the instruction to start the next preceding control process in register 2, one machine cycle of flip-flops 3 and 4 and the microinstruction when the logic is "1" is set. An example of a case where the same operation as in the second machine cycle is performed, and both flip-flops 3 and 4 are logic "1", the next instruction/interrupt processing execution start instruction is not invalidated, and the next instruction/interrupt processing execution start The same operation is performed except that instead of notifying that the instruction has been invalidated, the control circuit 7 is notified that the final step has been executed. The instruction will be executed as a microinstruction that should actually be executed. As a result, the start of the next instruction/interrupt process after this instruction/interrupt process will be delayed by one machine cycle.

If both flip-flops 3 and 4 are logic “0”,
The microinstruction held in register 1 will always be executed, resulting in normal microprogram performance.

As shown in the explanation of the operation in the above embodiment, the performance of the microprogram can be varied by the state values set in the flip-flops 3 and 4 and the microinstructions set in the register 2.

〔Effect of the invention〕

As explained above, the present invention can also be used as a speed regulating circuit for a microprogram by setting data as necessary in two flip-flops and one register from an external device. It can also be used as a debug circuit to check for interference in The effect is that it is possible to suppress a decrease in reliability, suppress a rise in equipment costs, and also to be able to control the speed of a microprogram with one microprogram, making microprogram management easier. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1, 2...Register, 3, 4...Flip-flop, 5-7...Control circuit, 8...
... Selector, 100-114 ... Signal line, 2
00-202...Scan signal line.

Claims (1)

[Claims] First and second flip-flops whose state values can be set separately by an external device, and a next preceding control process start instruction that instructs the preceding control device to start the next preceding control process. and a register in which an external device can set a microinstruction including a next instruction to be executed or a next instruction/interrupt processing execution start instruction for instructing the arithmetic execution unit to start interrupt processing; and a register for holding the first flip-flop. If the status value is set, the next preceding control processing start instruction held in the register is regarded as the true next preceding control processing start instruction, other next preceding control processing start instructions are invalidated, and the first preceding control processing start instruction is invalidated. If the state value held by the flip-flop is in the reset state, the first control circuit validates all next preceding control processing start instructions; and if the state value held by the second flip-flop is in the set state. , considers the next instruction/interrupt processing execution start instruction held in the register as a true next instruction/interrupt processing execution start instruction, invalidates the other next instruction/interrupt processing execution start instructions, and outputs the second flip-flop. When the state value held by is in the reset state, a second control circuit that validates all next instruction/interrupt processing execution start instructions, and the first and second control circuits start the next preceding control processing. When the instruction or the next instruction/interrupt processing execution start instruction is invalidated, the microinstruction held in the register is controlled to be executed after the final step of the currently executing instruction/interrupt processing execution control microprogram is executed. A microprogram control device comprising: a third control circuit.