KR0162462B1 - Device and method for driving microprocessor - Google Patents

Abstract

The present invention enables each program of the microprocessor to be executed independently, and stores the start address and the end address of each program to debug each program in the event of an error, thereby facilitating the program at a low time and at a low cost. It works.

Description

Microprocessor Drive and Driving Method

1 is a flow chart schematically showing a method for driving a microprocessor according to the prior art.

2 is a flow chart showing in detail a microprocessor driving method according to the prior art.

3 is a configuration diagram of a microprocessor driving apparatus according to the present invention.

4 is an operation waveform diagram of each part of the microprocessor driving apparatus according to the present invention.

5 is a flowchart illustrating a register input method according to a partial program at the time of reset among driving methods of a microprocessor driving apparatus according to the present invention.

6 is a flowchart illustrating a method for modifying a program counter value after reset among driving methods of a microprocessor driving apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

1,2,3: Register 4: Multiplexer

5: comparator 6: program counter

7,8,9: flip-flop

The present invention relates to a microprocessor (micro-processor), and in particular to a microprocessor for maximizing program development and debugging (debugging) efficiency by being able to process only a certain section of the program of the microprocessor (program); It relates to a driving method thereof.

In general, a microprocessor (micro-processor), starting with the program at the reset address (usually Φ address) and executes the program in the order of execution by the program counter (program counter).

That is, at the reset point, the program counter has a reset address. When the reset is completed, the microprocessor executes the program at the reset address, and simultaneously increases the value of the program counter to execute the program at the next address.

FIG. 1 illustrates a program execution flow of a microprocessor according to the related art, and the beginning of the program includes an initialization part for determining a register setting for a typical program execution or an input / output of a port.

When the initialization is completed as described above, the main program enters the main program. The main program can be divided into blocks from main program 1 to main program N by function.

FIG. 2 shows the program execution flow of the microprocessor in more detail. The program execution flow of the microprocessor starts from the first reset address as described above, and reaches the main program through several processes. Perform.

However, such a microprocessor, if a programmer develops a program having the same flow as FIG. 1 when developing a program, the programmer has to check all the steps of FIG. 1 again in order to debug an error in any program. do.

That is, in the conventional microprocessor, if an error occurs in the driving method, all driving programs should be checked. Therefore, when the driving program becomes large, debugging is very difficult, and even if debugging, human resources, time, and cost are required. There is a problem in that a great loss in terms of.

Accordingly, an object of the present invention, in order to solve the above problems, it is possible to run each program independently, and to store the start address and the end address of each program, which can be debugged by each program when an error occurs It is to provide a processor drive.

Another object of the present invention is to provide a method of driving a microprocessor driving apparatus for efficiently controlling the microprocessor driving apparatus.

The microprocessor driving apparatus of the present invention for achieving the above object comprises: a first register for storing the start address of the sub-program to be executed in the whole program, a second register for storing the end address of the initialization program; A third register for storing the end address of the program to be executed, a multiplexer for selectively outputting outputs of the second and third registers to a comparator according to an output signal of the first flip-flop, and an active port 0, 1, and 2 input the end address of the initialization program, the start address and the end address of the subprogram to the first to third registers, respectively. First to third three-phase buffers for use as general ports of the first address and start address values stored in the second register A program counter that increases a counter value when the program is input, a comparator for comparing the output of the program counter with the outputs of the second to third registers, and a cycle from the moment the program counter reaches the initial end address. The first flip-flop for outputting a high signal, the second flip-flop for applying a selection signal to the multiplexer according to the reset state of the microprocessor, and the end address of the third register and the counter value of the program counter become negative. And a third flip-flop for outputting a high signal to terminate the program execution mode.

In the method of driving the microprocessor driving apparatus of the present invention for achieving the above another object, only a partial program whether to perform the entire program after the initialization program during the initialization process and the program execution of the microprocessor consisting of a plurality of subprograms And a process of determining whether or not to perform the partial program and executing only the corresponding subprogram by inputting a start address and an end address of the corresponding subprogram.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 3, the microprocessor driving apparatus of the present invention includes an AND gate AND0 for inputting a Partial Program Run Mode Enable (PPRMEN) signal and a reset signal, and an output of the AND gate AND0. According to the three-phase buffer, the start address (START ADDRESS), the initial end address (INITIAL END ADDRESS), and the end address (END ADDRESS) of the subprogram to be executed from the ports 0, 1, and 2 are input. Three-phase buffers TB0 to TB2 to be output to the first to third registers 1, 2 and 3, or to be used as ports of the original microprocessor, and the second and third registers 2 and 3 And a comparator 5 for comparing the output of the < RTI ID = 0.0 >) < / RTI > with the value of the program counter 6 and the comparator 5 according to the output XYZ of the second flip-flop 9 from the second register and the third register. A multiplexer (4) for selectively outputting an input and said program count The first flip-flop 7, which outputs the high signal FLAG1, and the logical product of the output of the first flip-flop 7 and the clock signal for one period from the moment (6) reaches the initial end address are input. The second flip-flop 9 for outputting the selection signal XYZ to the multiplexer 4 and the output XYZ of the second flip-flop 9 is high (= 1). And a third flip-flop 8 which selects the output as the output of the third register and sets the output signal FLAG2 high when the program counter 6 is equal to this value to end the subprogram execution mode.

If the reset signal and the PPRMEN signal are both high in the driving device, the driving device operates in the sub program execution mode.

At each time point shown in FIG. 4, ① denotes a time point at which an initial end address value is equal to a count value of a program counter, and ② denotes a subprogram start address to be input to the program counter so that the count value increases as a program is executed. ③ is a time point at which the sub-program end address value is equal to the count value of the program counter, and ④ is a time point at which the internal reset (RST) becomes high to stop program execution. In more detail as follows.

First, as described above, the PPRMEN signal is inputted to 1, and the reset signal is inputted to 1 to reset the microprocessor, and the respective flip-flops and other registers are initialized by setting the internal reset signal RST to 1.

When the initial end address is input through the port φ, since the PPRMEN and the reset signal are high, the first to third three-phase buffers connected to each of the ports 0, 1, and 2 are activated to the first register 1. The data, i.e., the initial end address, is input.

This is to set register setting or input / output relationship of ports for initialization of a program, and is executed from the reset vector address to the initial end address.

If the initialization program part is not necessary, the initial end address may be input as φφφH, wherein the initial end address is input to the upper byte of the first register if the BYTE CON signal is 1, and to the lower byte if φ.

The second register 2 is inputted with a start address of a sub-program to be executed among all programs through port 1 while the first to third three-phase buffers are activated.

In this case, like the first register, if the BYTE CON signal is 1, the signal is input to the upper byte of the second register, and if φ is input to the lower byte.

The third register 3 inputs the end address of the sub-program to be executed among the entire programs through the port 2 when the first to third three-phase buffers are activated, and inputs the upper byte and the high byte. As with the first and second registers, is determined by the BYTE CON signal.

As described above, when each address is input from each of the ports 0, 1, and 2 to the first to third registers, a reset signal is output as φ to execute the microprocessor.

By outputting the reset signal as φ as described above, the first to third three-phase buffers are inactive, thereby enabling the ports 0, 1, and 2 to be used as general ports of the microprocessor, and the program counter 6 Since the internal reset signal becomes φ, start from the reset address (usually φφφH).

On the other hand, the output signal XYZ of the second flip-flop 9 outputs a low signal when the internal reset is performed. Accordingly, the multiplexer 4 compares the initial end address stored in the input Iφ, that is, the second register. Output to one side of (5).

On the other side of the comparator 5, the count value of the program counter 6 is inputted to check whether it reaches the initial end address starting from the reset address.

Here, when the count value of the program counter 6 is equal to the initial end address, the comparator 5 outputs a high signal and connects the three-phase buffer connected between the comparator 5 and the first flip-flop 7. Since the output XYZ of the second flip-flop, which is an enable signal of TB3), is low, the output FLAG1 of the first flip-flop 7 becomes 1.

If the output FLAG1 of the first flip-flop 7 is 1, the output of the AND gate AND1 is enabled according to the clock signal to change XYZ, which is the output of the second flip-flop 9 to 1, accordingly. The clear signal CLR of the first flip-flop 7 is enabled, and the output of the first flip-flop 7 is changed back to zero.

That is, the output FLAG1 of the first flip-flop 7 becomes 1 for one clock period from the moment when the program counter 6 reaches the initial end address, during which the PPRMEN signal and the FLAG1 signal are input. The output of the AND gate AND2 is 1, and the start address of the subprogram input to the first register is input and set to the program counter 6 to execute the program from this address.

In addition, since the output XYZ of the second flip-flop becomes 1, the output of the multiplexer becomes I1, that is, the end address of the subprogram input to the third register, and the comparator 5 is connected to the end address of the subprogram. It checks whether the end address is inputted to the end address from the start address of the subprogram output from the program counter, and executes only the subprogram to be executed among the entire programs.

Subsequently, when the count value of the program counter is equal to the end address of the subprogram, the comparator 5 outputs a high signal, and since the XYZ signal is also high, the FLAG2 signal that is the output of the third flip-flop 8 is 1. In this manner, the microprocessor is brought into an internal reset state through the OR gate OR1 to terminate the subprogram execution mode.

That is, in the present invention, as shown in FIG. 5 during operation, after resetting the microprocessor in relation to the execution of the subprogram at reset, the initial end address and the start address and end address of the subprogram are input to each register. After releasing the reset of the microprocessor, as shown in FIG. 6, if the program counter value is not the initial end address value, the program counter value is set to the initial end address. The subprogram is executed until the end address of the subprogram is set by setting the address value and increasing the program counter value.

At this time, when jumping to a program out of range by a conditional instruction and an unconditional instruction during program execution within the start address and end address range of the subprogram, the subprogram mode does not support it. The end address must be adjusted in anticipation.

When a program outside the range of the subprogram is called by a CALL instruction, the subprogram is supported in subprogram mode to execute the subprogram again after executing the called program, and in the case of an INTERUPT, In order to process this by interruption, a program outside the start address and end address range is called. Therefore, the program is supported in the subprogram mode and the subprogram is executed again after executing the program outside the range.

On the other hand, when the subprogram execution mode becomes an error state due to a conditional jump or an unconditional jump, the PPRMEN signal is output low to notify the external occurrence of an error and go to the processor reset state, and if the subprogram execution mode is not operated, the PPRMEN The signal is pulled low and reset to allow the microprocessor to operate in the normal program execution mode to have a microprocessor program flow.

As described above, according to the present invention, each program can be executed independently, and the start address and the end address of each program can be stored to debug the program for each program in the event of an error, thereby facilitating the program at a low time and a low cost. It can be effective.

Claims (2)

A first register for storing the start address of the subprogram to be executed among all programs, a second register for storing the end address of the initialization program, and a third for storing the end address of the program to be executed A multiplexer for selectively outputting the outputs of the second and third registers to the comparator in accordance with a register and an output signal of the second flip-flop, and through the ports 0, 1, 2 during active operation to the first to third registers. First to third three-phase buffers for inputting the end address of the initialization program, the start address and the end address of the subprogram, and the ports 1, 2, and 3 to be used as general ports of the microprocessor during inactivity. And a program car that increases a counter value according to program execution when a start address value stored in the second register is input. A comparator for comparing the counter with the output of the program counter and the outputs of the second to third registers, a first flip-flop that outputs a high signal for one period from the moment the program counter reaches the initial end address; A second flip-flop for applying a selection signal to the multiplexer according to the reset state of the microprocessor; and a high signal for terminating the sub-program execution mode when the end address of the third register is equal to the counter value of the program counter. And a third flip-flop. Determining whether to perform all programs or only some sub-programs after performing the initialization program, when performing the initialization process, the microprocessor consisting of a plurality of sub-programs; And inputting a start address and an end address of a program to perform only a corresponding subprogram.