JPS59121440A - Integration circuit - Google Patents

Abstract

PURPOSE:To test the executing operation without having no complicated branching operation by using a run program stored in an ROM as a test program and using the control data substituting the state of a condition code as a branch instruction. CONSTITUTION:A run program is stored in an ROM1, and this ROM1 is actuated by the state of a condition code and in a run mode including an instruction with which the branching is decided. A processor 3 is provided to an integration circuit which is equal to the ROM1, and a test control circuit 8 is connected to the processor 3. Then a test mode is set by the terminals 13 and 14 which are connected to the outside. Thus it is possible to execute successively the run program of the ROM1 through the processor 3. The operation of a specific instruction is controlled by a selector 25 on the basis of the control data given from the circuit 8 when the specific instruction is decoded by a decoder 21 during execution of an instruction. Thus an executing operation is tested with no complicated branching operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a means for easily performing an instruction execution test of an integrated circuit body comprising a processor equipped with a ROM storing a Langlogram, and is integrated with the integrated circuit body. Concerning highly practical integrated circuits.

[Technical background of the invention and its problems]

2. Description of the Related Art With the development of integrated circuit technology, many integrated circuits have been developed in which program-controlled processors are highly functional and highly integrated into a so-called single chip. Furthermore, in recent years, ROM that stores program instructions responsible for the operation of the processor
An integrated circuit in which a read-only memory (read-only memory) is integrated with the above-mentioned devices has also been developed. Like this RO
Also, unlike conventional integrated circuits, integrated circuits consisting of processors do not require external connection terminals, rear address output terminals, command input terminals, etc. for supplying program instructions and executing them. Therefore, the number of terminals required by the integrated circuit can be significantly reduced, resulting in a significant effect in reducing the size and cost of the integrated circuit.

Now, when testing the operational functions of the integrated processor as described above, conventionally, the instructions to be tested are externally given to the processor one by one, and the execution results of the instructions are obtained to determine whether the instructions are good or not. is being determined. However, in an integrated circuit consisting of a processor equipped with an internal ROM, instructions are given internally, so
As mentioned above, the test method described above cannot be used because no terminal is prepared for giving commands from the outside. Therefore, some ideas have been devised, such as using terminals used for purposes other than command input when the processor is in run mode for command input during test mode, and switching the signal path internally to enable command input. ing.

However, since one terminal serves multiple functions, there is a problem in that the test method becomes complicated.

Moreover, if the number of terminals available for inputting instructions is small, it is necessary to input one instruction over several cycles, and furthermore, the test is executed by giving instructions one by one. There was a problem in that it required a long time.

In addition, when inputting an instruction in this way, it may be necessary to give data for the original function to the instruction input terminal when executing the instruction, so when executing the above instruction, it is necessary to input data for the original function at least one cycle before It is necessary to give commands. This means that part of the operation related to the instruction to be tested begins before the instruction is executed, and therefore, the AC characteristics test, or the test to check whether the instruction operates correctly within one cycle, is performed. etc. could not be done.

In addition, with the development of integrated circuit technology, one instruction has come to have a field consisting of multiple operands in addition to the operation. , 4 to 16 addressing methods can be selected.

Therefore, if we try to test all combinations of functions that operations and operands have, the number of test items becomes extremely large. Considering these circumstances;
Generally, each field is tested separately, but there is a problem in that it is not possible to test for failures that occur for the first time due to a combination of several fields. Ta. In addition, there are other problems such as if test data or a test program is prepared for only one strain and a test is performed, it is not possible to discover failures related to data values. Therefore, R
It has not been possible to effectively test the operation of an integrated circuit consisting of a processor equipped with OM.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to simplify the operational functions of an integrated circuit main body consisting of a processor equipped with a ROM that stores a run program that operates in run mode. It is an object of the present invention to provide a highly practical integrated circuit in which means capable of efficiently testing are integrated together with the integrated circuit main body.

[Summary of the invention]

The present invention provides means for setting a test mode for an integrated circuit main body consisting of a processor equipped with a ROM, means for externally providing control data related to test operation control of a specific instruction, and A means for executing program instructions and controlling the operation of the specific instruction according to the control data when the specific instruction is decoded during execution of the instruction is integrated with the integrated circuit main body, and is integrated with the integrated circuit main body. The control data is used in place of the condition code to control the operation of a branch instruction whose branch is determined by a condition code.

〔Effect of the invention〕

Therefore, according to the present invention, since the run program in the ROM is treated as a test program and the instruction execution test is performed by the processor, there is no need to provide instructions from the outside, and therefore the test can be performed easily and at high speed. Moreover, since the execution of branch instructions within a program can be controlled using control data, only necessary tests can be performed regardless of the original flow of the program. For this reason, test data can be easily created and required tests can be carried out reliably, resulting in great practical effects.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an integrated circuit according to an embodiment. In the figure, 1 is a ROM (read-only memory) that stores a run program that operates in a run mode. This ROM 1
The command of the run program read from the above is set in the command register 2 as the command currently being executed, and the processor 3 operates in response to this command. This Zorosessa 3 is
Mainly used for accumulators, general registers, and calculations.
It is comprised of an ALU, a random access memory (RAM), and the like, and executes predetermined arithmetic processing according to instructions set in the instruction register 2. At this time, the sole processor 3 inputs the data given from the data input terminal 4,
The above-mentioned predetermined processing is executed and the execution results are outputted via the data output terminal 5. Further, in the figure, reference numeral 6 indicates address data, and the address data for the ROM 1 of the next instruction scheduled to be executed is stored, and this is a trap to be applied to the address terminal of the ROM 1. These constitute the integrated circuit body.

In contrast to such an integrated circuit main body, the present integrated circuit is constructed by integrating the test control circuit 8 and its peripheral circuits. The test control circuit 8 sets a test mode for the integrated circuit body and generates various test control signals. That is, the test control circuit 8 includes a test notification flip-flop fil and a test execution control flop 12, and controls the entire test execution. The test notification flip-flop 11 is a D-type flip-flop, and is set by receiving a test mode signal applied to a terminal 13 at its D input, and receiving a test execution signal applied to a terminal 14 at its clock terminal. The Q output of this clip floor sensor 1 is input to the J terminal of a test execution flop 12 which is a flip-flop at J-, and is input to the J terminal of the test execution flop 12 which is a flip-flop. Set 12. By setting the test execution 7 processor 12, a test mode is set for the main body of the integrated circuit including the processor 3. Further, the test execution control flop 12 is reset by receiving the following M number of a test stop counter 16, which is a down counter, into which the number of test execution steps is preset via the data input terminal 4. Testos above) 7 deca
The counter 16 is for counting down the data set in response to the above-mentioned clock. Therefore, when the instruction test of a predetermined number of steps is completed, the test execution flop 12 is reset. ,
Test mode is released. The Q output of the test execution flip-flop 12 is applied to the output circuit 3 and also to the test notification flip-flop 70 block 11 to reset it. In other words,
- By setting the test execution flip-flop 12, the test notification flip-flop 11 is set. ``The test control circuit 8 is also provided with a branch shifter 17 consisting of a shift register. This branch shifter 17 presets, for example, data "1" specifying a branch and data "0" blocking a branch in the node, and as described later, each time a branch instruction is decoded in the processor 3, the branch shifter 17 decodes the branch instruction. A signal is inputted through an AND circuit 18, which serially outputs data specifying whether or not to perform the above-mentioned branching. Furthermore, the test control circuit 8 is provided with an AND circuit 19 that receives the test mode signal and the mutual output of the test execution flip-flop 12. By this output, a signal is output that defines the period from when the test mode signal is applied until the start of test execution as a test preparation period.

By the way, the processor 3 is provided with a decoder 21 that decodes the operation code 2a of the instruction set in the instruction renoster 2.
Decoded outputs obtained by decoding various branch instructions are extracted via an OR circuit 22. As a result, it is detected that the instruction currently being executed is a branch instruction.

The output of this OR circuit 22 is applied to the AND circuit 18 of the test control circuit 8. Further, when the instruction stored in the instruction register 2 is a branch instruction, the branch condition 7A-LD indicating the branch condition is stored in the logic circuit 2 of the processor 2.
given to 3. This logic circuit 23 inputs the condition code of the status register 24 which stores the internal state of the integrated circuit main body, and determines whether or not to branch according to the above-mentioned branch condition. This logic circuit 2
In the run mode, branch control is performed according to the state of the condition code by the output of 3. Therefore, the output of the logic circuit 23 is given to the selector 25,
The output is selected between the output from the branch shifter 12 and the Q output of the flip-flop 12. In run mode, logic circuit 2
3 is selected, and in the test mode, the signal from the branch shifter 17 is selectively output in place of the output of the logic circuit 23. Finally, during test execution, control of branch instructions according to the state of the condition code is controlled by the signal obtained from the branch shifter 17. A signal selected via this selector 25 is output via an AND circuit 26 when a branch instruction is decoded.

On the other hand, the address data set in the address register 6 is controlled as follows.

Two stage selectors 27 and 28 are provided at the input stage of the address register 6, and the address data given from the data input terminal 4 is set during the test preparation period by the output of the AND circuit 19. It has become. Further, when an instruction is executed, the selector 27 is switched and internally generated address data selected by the second stage selector 21jK is set. This second stage selector 27 operates upon receiving a signal from the AND circuit 26 when decoding the branch instruction, and when there is a branch instruction, the branch destination address data 2C set in the instruction register 2 is selected. If there is no branch instruction, the output of the count amplifier circuit 29, which is obtained by incrementing the address data set in the address register 6 by one address, is selected. As a result, the instructions in ROM 1 are controlled to be executed one by one in sequence. Similarly, the address data set in the address register 6 is outputted from the data output terminal 5 via the converter cover 7, for example, at the end of test execution.

The integrated circuit according to this embodiment is constructed by integrating the test control circuit 8 for test execution and its peripheral circuits together with the integrated circuit main body as described above.

Incidentally, the ROM J stores in advance a run program as shown in FIG. 2, for example. What is shown in FIG. 2 is a Langlogram from address 101 to address 202. At address 101, a load instruction to load the general register GROK7'-INTER1000J of processor 3 is stored. Sarimata 10202,
Data and data stored in the general register GRO
1'' and stores the result in the general register GR1.

Also, although the instructions at addresses 10303 and 10707 are omitted, it is assumed that no branch instructions are included here.

Then, a subtraction instruction to subtract data r1234J from the data in general register GR15 at address 10808 and store the result in general register GRO is executed again at address 10909, the previous instruction, and at address 108. A conditional branch instruction is stored that indicates that if the execution result of the received instruction is not zero, the program will branch to address 20,000, and if it is zero, the program will proceed to the next address, that is, address 110.

Then, the address 20000 and instruction is registered, and 201
01 address 20000 address If the execution result of the instruction is zero, it branches to address 210, and if it is not zero, the trap is the next 2020 address.
A branch instruction instructing to go to address 2 is stored. However, 17a.

Reference numeral 17b indicates control data output from the branch shifter 17 in place of the output from the logic circuit 23 according to the state of the condition code each time a branch instruction is decoded. When the branch instruction is executed for the second time, it is indicated that the branch is not to be executed.

When testing the instruction execution operation of the integrated circuit main body formed by storing such a Langrodorum in the ROM 1, the test is performed, for example, as follows. That is, first, a test mode signal is applied to the terminal 13. As a result, since the test execution frizz 7° 12 is in the reset state, the test preparation mode is set as the output of the AND circuit 19.

In this state, initial data for testing is set in the accumulator, general register, etc. inside the processor 2 via the data input terminal 4.

Next, the address register 6 is set with the start address data of the instruction to be tested, the counter 16 is set with the number of test instruction steps, and the branch shifter 17 is set with control data for controlling branching. All of these are performed by inputting each data via the data input terminal 4, thereby completing preparation for the test.

Afterwards, when a test execution signal is input to terminal 14,
The test notification frizzo flop 1 is set, and then, in synchronization with the clock signal input from the terminal 15, the test execution frizzo flop f12 is set. This will start the test. The test is performed using the address data set in the address register 6.
This is done by accessing the address and setting the instruction stored at that address in the instruction register 2. At this time, if the instruction is not a branch instruction, the instruction is executed by the processor 3 as is. Thereafter, in response to the next clock, the next instruction is read out and executed using the address data newly set in the address register 6 indicating the next address. This process is executed repeatedly in sequence. However, if the instruction to be executed now is a branch instruction, the decoder 21
decodes this and provides a clock to the branch shifter 17. As a result, control data is provided from the branch shifter 17, and whether or not to branch is controlled according to this control data. The address data of the branch destination set in the instruction register 2 is set in the address register 6, or the address data indicating the next address obtained by the count up circuit 29 is set in the address counter 6. Control takes place.

When such instructions are executed one after another and the output of the counter 16 counts down each time the instructions are executed for the preset number of instruction execution steps, the test execution flip-flop 12 is reset and the test is started. ends. Thereafter, various data contents of the accumulator, etc., address data set in the address register 6, etc. are read out via the data output terminal 5 and checked, thereby determining whether the execution operation is good or bad. become. In this way, for example RO
By dividing the instruction address areas in M1 and testing all of them, it is possible to reliably inspect whether the integrated circuit itself is good or bad.

As described above, according to the present invention, the Langlogram stored in ROM J is treated as a test gramogram, and for branch instructions, it is possible to prevent complicated branches by giving control data that changes to the state of the condition code. You can test its execution behavior without any need. Therefore, it is possible to continuously test instruction operations in units of, for example, several steps to several tens of steps, thereby significantly shortening the time required for the test and increasing test efficiency.

Furthermore, since the flow of branch instructions can be controlled by externally set control data, only the necessary tests can be performed efficiently without forming multiple loops.

Therefore, it is possible to easily analyze the program and create test data based on the results of this analysis, and also to easily consider the test results. Therefore, it is possible to conduct a simple, efficient, and highly reliable test, which has a great practical effect.

Note that the present invention is not limited to the above embodiments. For example, as shown in FIG.
It is also possible to directly give external control data via the external controller. In this way, it is possible to test whether or not to execute an instruction based on the input/output state of Ilo, etc., and even more effects can be expected. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between an example of a program stored in a ROM and control data for branch instructions, and FIG. 3 is a modification of the present invention. It is a main part configuration diagram showing the. DESCRIPTION OF SYMBOLS 1... ROM, 2... Instruction register, 3... Processor, 4... Data input terminal, 5... Data output terminal, 6... Address register, 7... Output huffer, 8 . . . Test control circuit, 1 No. . . . Test notification frizzo flop, 12 . Branch shifter, 18°19...AND circuit, 21...decoder, 22...
・OR circuit, 23...Logic circuit, 24...Status register, 25, 27.28...Selector, 2
6...AND circuit, -29...counter, f circuit. Applicant's representative Patent attorney Takehiko Suzue 1, 2, 3, Director of the Patent Office Kazuo Wakasugi, Indication of the case, Patent Application No. 57-227711 2, Name of the invention, Integrated circuit 3, Amendment. Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent 5, Voluntary amendment - '', Contents of the amendment (11 Specification, page 14, line 9, ``Output buffer 7'')
Before the phrase ``from output selector Iσ'' is added. (2) Same, page 18, lines 3 to 6, “Decoder 21
This control data j is corrected to read "control r output by the branch shifter 17". (3) In the same line, the 18th negative 12th line says ``Control is performed. Add all the sentences that say "It will be done." (4) The drawing and Figure 1 will be corrected as shown in the attached sheet.

Claims (3)

[Claims] (1) A test mode is set for nine integrated circuit main bodies consisting of a processor equipped with a ROM storing a runnogram that operates in a run mode consisting of instructions including branch instructions in which branching is determined by the state of a condition code. means for externally providing control data related to operation control of a specific instruction when setting the test mode; and means for sequentially executing one or more instructions of the run program in the ROM when setting the test mode; An integrated circuit comprising: means for controlling the operation of the specific instruction according to the control data when the specific instruction is decoded during execution of the instruction; and a means for controlling the operation of the specific instruction according to the control data. (2) The fixed instruction is a branch instruction that determines whether to branch according to the state of a condition code, and the control data is given to the branch instruction instead of the condition code. The integrated circuit according to item 1. (3) The integrated circuit according to claim 1, wherein the control data applied from the outside is stored and retained during the test mode.